2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON) 2020
DOI: 10.1109/upcon50219.2020.9376407
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Parity Generator & Parity Checker Using Sub-threshold Adiabatic Logic

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Cited by 3 publications
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“…As soon as the packet synchronism is done, parity checks help detect errors in the receiver's output [23]. Authors [25] have proposed a parity generator circuit design using quantum-dot cellular automata. This technology has a low area and low power requirements but is challenging to implement.…”
Section: Application To Parity Generator and Checkermentioning
confidence: 99%
“…As soon as the packet synchronism is done, parity checks help detect errors in the receiver's output [23]. Authors [25] have proposed a parity generator circuit design using quantum-dot cellular automata. This technology has a low area and low power requirements but is challenging to implement.…”
Section: Application To Parity Generator and Checkermentioning
confidence: 99%