Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs Beyond 7nm

Wu, Heng; Gaidai, Oleg; Tsutsui, Gen; Niu, C.; Brew, Kevin; Durfee, Curtis; Prindle, C.; Kamineni, V.; Mochizuki, Seibu; Lavoie, C.; Nowak, E.; Liu, Z.; Yang, Jie; Choi, S.; Demarest, J.; Lan, Yu; Carr, Adra; Wang, W.; Strane, J.; Tsai, Stan; Liang, Yangyang; Amanapu, H. P.; Saraf, Iqbal; Ryan, Kevin; Lie, Fee Li; Kleemeier, W.; Choi, K.; Cave, N.; Yamashita, T.; Knorr, A.; Gupta, Divya; Haran, Bala; Guo, Dechao; Bu, H.; Khare, Mukesh

doi:10.1109/iedm.2018.8614661

Cited by 28 publications

(17 citation statements)

References 2 publications

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“…Interfacial layer (IL), HfO 2 , and low-k spacer regions have the dielectric constants of 3.9, 22.0, and 5.0, respectively. Contact resistivity at S/D and silicide interface is fixed to 10 −9 Ω•cm 2 [25]. Equivalent oxide thickness (EOT) is 1.0 nm, which consists of 0.7-nm-thick IL and 1.7-nm-thick HfO 2 .…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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“…In addition, the dielectric constants of the interfacial layer (SiO2), spacer, and high-k dielectric (HfO2) were 3.9, 3.9, and 22.0, respectively. Contact resistivity of the wrap-around contact was 10 −9 Ω•cm 2 [27], and operation voltage (VDD) was 0.7 V. The on-state condition was defined as the gate (Vgs) and drain voltages (Vds) of the VDD and the off-state condition was defined as the Vgs of 0 and the Vds of the VDD.…”

Section: Simulation Structures and Methodologymentioning

confidence: 99%

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

2021

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Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress (SZZ) predominantly causes variations of on-state current (ΔIon). NSFETs exhibit the greater ΔIon than FinFETs because electron velocities and densities in channels vary with respect to SZZ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents (Icap, Ib-b). NSFETs exhibit the greater |Icap|/Ion than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the |Ib-b|/Ion is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases |Ib-b|/Ion only, but short rise time of TSV signals increases both |Icap|/Ion and |Ib-b|/Ion. Unfortunately, conventional devices cannot satisfy criterion for analog applications (|Icap, Ib-b|/Ion< 0.5%); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The |Icap|/Ion for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The |Ib-b|/Ion for NSFETs decreases remarkably due to completely blocked Ib-b path, but FinFETs still have Ib-b path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.

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“…Doping concentrations of S/D and punch-through-stopper are 2×10 20 and 2×10 18 cm -3 , respectively. Contact resistivity at the S/D is fixed to 10 -9 Ω•cm 2 [16]. Dielectric constants of interfacial layer (IL), high-k, and low-k spacer regions are 3.9, 22.0, and 9.0, respectively.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

Yoon

Baek

2020

IEEE Access

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A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (G m) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (R o) by dual-WF scheme and thus achieve larger intrinsic gain (A V = G m R o). Smaller G m and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large R o increases the maximum frequency (F max). Especially, 2-CAS has larger A V and F max than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs Beyond 7nm

Cited by 28 publications

References 2 publications

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

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