Parasitic extraction: current state of the art and future trends

Kao, W.H.; Lo, Chi-Yuan; Basel, M.; Singh, Raminderpal

doi:10.1109/5.929651

Cited by 78 publications

(21 citation statements)

References 63 publications

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“…The current parasitic extraction tools fail to meet RF IC design requirements for fully integrated parasitic models. The interconnect and interaction parasitic impedances significantly affect electrical issues, including matching, noise, frequency shift, timing, electromigration, signal integrity, and power supply integrity [27]. Because of the arisen deviation in measured results particularly the measured operating frequency, we were inclined to use EM solvers rather than convention parasitic extractors.…”

Section: Circuit Design and Implementationmentioning

confidence: 99%

Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success

et al. 2016

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Section: Circuit Design and Implementationmentioning

confidence: 99%

Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success

et al. 2016

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“…In general, field solvers can not be used for full-chip RCL extraction, being too compute intensive, and the Monte-Carlo based statistical field solver QuickCap [13] is suitable only for net-by-net analysis in a chip, as it does not involve any meshing. The most commonly used approaches for extracting R and C at the full-chip level are pattern matching using look-up tables, and the even more accurate context-based method that looks at each conductor with in context of its 3D surroundings [14]. The Cadence Fire & Ice® based methodology, which uses a context-based modeling approach, is discussed in reference [12].…”

Section: Capacitance Modelingmentioning

confidence: 99%

Modeling and characterization of copper interconnects for SoC design

Arora

2003

International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003.

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Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper we discusses the Cu process and its impact on modeling the interconnect parasitic elements -resistance (R), capacitance (C), and inductance (L). For a given process node, use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. Impact of the X-Architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length to an average of 20%, is also discussed. Finally, silicon validation of interconnect R,C, and L model using a test-chip approach is covered.

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“…Until recently, the mainstream EDA industry was concerned primarily with on-chip electrical design and performance verification issues. More specifically, modeling of interconnect parasitics was driven primarily by on-chip interconnect capacitance extraction and computation for the purpose of accurate timing analysis, static noise calculation, and a variety of other functionality checks [5]- [10]. However, as circuit density, on-chip functionality, and switching speed continue to increase, so does the complexity of the interconnect structure and its electrical behavior.…”

Section: A Modeling Approachesmentioning

confidence: 99%

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

2001

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The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance-and/or portability-driven, multifunctional ULSI systems.

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Parasitic extraction: current state of the art and future trends

Cited by 78 publications

References 63 publications

Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success

Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success

Modeling and characterization of copper interconnects for SoC design

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

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