Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing

Hsiao, Vincent Wei-Hao; Lin, Chun-Yu; Chen, Nai-Chen

doi:10.1109/tcad.2017.2685598

Cited by 17 publications

(3 citation statements)

References 15 publications

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“…In order to minimize the parasitic capacitors and mismatch for the capacitance array layout, automatically generating the optimal placement and routing result is of necessity. [11] has implemented related layout generation, however it may not be used in async SAR ADC, and a special requirement of array/line shape instead of a square layout is a must. Therefore, developing a framework which can generate a needed layout with good balance between parasitic capacitance and matching would be required.…”

Section: Capacitor Layout For Async Sar Adcmentioning

confidence: 99%

On EDA solutions for reconfigurable memory-centric AI edge applications

Chen

Chang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Capacitor Layout For Async Sar Adcmentioning

confidence: 99%

On EDA solutions for reconfigurable memory-centric AI edge applications

Chen

Chang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…The common-centroid routing technique is adopted in the charge-scaling digital-to-analog converter (DAC) of the ADC. Common-centroid placement alleviates the systematic mismatches as well as the parasitic capacitance, which is induced in the layout [48,49]. Poly layers are used instead of metal layers to prevent the charges from getting lost to the substrate.…”

Section: Introductionmentioning

confidence: 99%

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Biswas

Mahbub

2021

Electronics

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This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.

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“…The reduction of mismatch in capacitor arrays due to interconnects in an ongoing area of research, and applying techniques such as those proposed in [30] and [31] would help mitigate this issue. As with [3], one advantage of this capacitor array over a typical binary-weighted array is that only the parasitics on the top plates of the capacitors are of concern since there are no switches on the bottom plate.…”

Section: Effective Number Of Bitsmentioning

confidence: 99%

Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC

Berton¹

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A 10-bit successive approximation register (SAR) analog to digital converter (ADC) was designed in a 130 nm CMOS process. The reference voltage generator in the ADC is made with an array of 25 unit capacitors, in comparison to binary-weighted SAR ADCs, which would use 1024 unit capacitors. The capacitor array is controlled using a state machine whose logic was determined and automatically generated using a recursive backtracking algorithm. Schematic-level simulation results for the ADC predict an effective number of bits (ENOB) of 9.39, worst case integral non-linearity (INL) and differential non-linearity (DNL) of 1.15 and 1 least significant bit (LSB), respectively, and average power consumption of 1.65 µW at 10 kSps. The Walden figure of merit is calculated to be 246 fJ/conv-step. The core layout area is 0.458 mm 2 .

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Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing

Cited by 17 publications

References 15 publications

On EDA solutions for reconfigurable memory-centric AI edge applications

On EDA solutions for reconfigurable memory-centric AI edge applications

A 2.53 NEF 8-bit 10 kS/s 0.5 μm CMOS Neural Recording Read-Out Circuit with High Linearity for Neuromodulation Implants

Backtracking Algorithm-Aided Design of a 10-Bit SAR ADC

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