No abstract

A 10-bit successive approximation register (SAR) analog to digital converter (ADC) was designed in a 130 nm CMOS process. The reference voltage generator in the ADC is made with an array of 25 unit capacitors, in comparison to binary-weighted SAR ADCs, which would use 1024 unit capacitors. The capacitor array is controlled using a state machine whose logic was determined and automatically generated using a recursive backtracking algorithm. Schematic-level simulation results for the ADC predict an effective number of bits (ENOB) of 9.39, worst case integral non-linearity (INL) and differential non-linearity (DNL) of 1.15 and 1 least significant bit (LSB), respectively, and average power consumption of 1.65 µW at 10 kSps. The Walden figure of merit is calculated to be 246 fJ/conv-step. The core layout area is 0.458 mm 2 .