New Charge-Steering DFEs in 55-nm CMOS

Pike, Jacob; Parvizi, Mahdi; Berton, David; Ben-Hamida, Naim; Aouini, Sadok; Plett, C.

doi:10.1109/tcsii.2020.3008059

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…On the other hand, LE amplifies the noise and signal together, which does not improve the BER performance of the communication system [14,15,16]. Based on the above reasons, DFE is mainly used to eliminate residual ISI together with LE [17,18]. DFE only amplifies the signal but not the noise, which can effectively improve SNR characteristic.…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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