In this paper, automatic parameter extraction techniques of Agilent's IC-CAP modeling package are presented to extract our explicit compact model parameters. This model is developed based on a surface potential model and coded in Verilog-A. The model has been adapted to Trigate MOSFETs, includes short channel effects (SCEs) and allows accurate simulations of the device characteristics. The parameter extraction routines provide an effective way to extract the model parameters. The techniques minimize the discrepancy and error between the simulation results and the available experimental data for more accurate parameter values and reliable circuit simulation. Behavior of the second derivative of the drain current is also verified and proves to be accurate and continuous through the different operating regimes. The results show good agreement with measured transistor characteristics under different conditions and through all operating regimes.
In this paper, automatic parameter extraction techniques of Agilent's IC-CAP modeling package are presented to extract our explicit compact model parameters. This model is developed based on a surface potential model and coded in Verilog-A. The model has been adapted to Trigate MOSFETs, includes short channel effects (SCEs) and allows accurate simulations of the device characteristics. The parameter extraction routines provide an effective way to extract the model parameters. The techniques minimize the discrepancy and error between the simulation results and the available experimental data for more accurate parameter values and reliable circuit simulation. Behavior of the second derivative of the drain current is also verified and proves to be accurate and continuous through the different operating regimes. The results show good agreement with measured transistor characteristics under different conditions and through all operating regimes.
“…Algorithms used to solve the optimization problem are either gradient-based (e.g., Levenberg-Marquardt) or gradient-free (e.g., Genetic Algorithm -GA). GA mimics the natural selection and evolution process and is more likely to find the global minimum [2]. All these minimization methods are iterative, and defining an appropriate starting point and parameter bounds is of crucial importance and requires considerable experience.…”
In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of an entire set of MOSFET model parameters using limited and incomplete IV measurements from on-chip monitor circuits. An important step in this method is the use of maximum-a-posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction could also be used to characterize the statistical variations of MOSFETs with the significant benefit that some constraints required by the backward propagation of variance (BPV) method are relaxed.
“…To address these challenges, researchers have delved into various optimization-based techniques for parameter extraction, including the application of genetic algorithms (GA) [1][2][3] and the implementation of deep learning methodologies (DL) [4][5][6][7][8][9].…”
Accurate current-voltage (I-V) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, the current BSIM model does not support a buried-channel-array transistor (BCAT), which is the structure of the state-of-theart commercial dynamic random access memory (DRAM) cell transistor. In this work, we propose an intelligent I-V modeling technique that combines genetic algorithm (GA) and deep learning (DL). This hybrid technique facilitates both optimization of BSIM parameter and accurate I-V modeling, even for devices not originally supported by BSIM. Additionally, we extended application of the DL to model one of the principal degradation mechanisms of transistor, the hot-carrier degradation (HCD). The successful modeling results of I-V characteristic and device degradation demonstrated that devices not supported by BSIM can be accurately modeled for integrated circuit simulations.
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