Parameter extraction and modelling of the MOS transistor by an equivalent resistance

Sharroush, Sherif M.; Abdalla, Yasser S.

doi:10.1080/13873954.2020.1857790

Cited by 4 publications

(2 citation statements)

References 32 publications

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“…After designing the circuit, this article will reduce the power consumption of the circuit by increasing the minimum delay of the minimum energy delay ratio topology by 50%. "Delay" refers to the propagation delay caused by the critical path of the circuit, and "energy" refers to the total energy extracted from VDD, including the output [10]. Therefore, to optimize the circuit, it is necessary to first find the critical path of the circuit.…”

Section: Critical Path Analysismentioning

confidence: 99%

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Wen

2024

ACE

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To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

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Section: Critical Path Analysismentioning

confidence: 99%

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Wen

2024

ACE

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“…To establish the gate sizes that minimize the critical path delay, we first compute the maximum delay of the circuit focusing on the critical path and minimize it using Gate Sizing without considering the branches. [13] With the logic efforts, electrical efforts, and the critical path of our design, the design estimates the propagation delay. [ ) is the ratio of the width and length of the channel of NMOS(PMOS).…”

Section: Critical Path Delay Optimizingmentioning

confidence: 99%

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

2023

J. Phys.: Conf. Ser.

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With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one of the most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in the paper, which comprises three types of architecture. The first design is using combinational logic circuit through a truth table of the absolute value of 2′s complement format and a comparator; the second design is a combination of a series of half adders and transmission gates and a comparator; the third design consists of a combinational logic circuit by truth table of 2′s complement and a cascade of full adders. Then the paper compares the total number of stages and consuming transistors of each circuit, and finally chooses the second circuit, which has five stages and 74 transistors of consumption, as the object of following optimization of critical path delay and energy consumption. With gate sizing, the optimized critical path delay is about 43.05 tp0. The original energy consumption under minimum delay is 49.88C, and the optimized energy consumption under 1.5x minimum delay is 30.35C which is reduced by 39.16%. The processing of the functional realization and circuit optimization of absolute-value detectors can both benefit from the design presented in this work.

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Optimum sizing of the sleep transistor in MTCMOS technology

Sharroush

Abdalla

2021

AEU - International Journal of Electronics and Communications

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Parameter extraction and modelling of the MOS transistor by an equivalent resistance

Cited by 4 publications

References 32 publications

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

Optimum sizing of the sleep transistor in MTCMOS technology

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