Optimum sizing of the sleep transistor in MTCMOS technology

Sharroush, Sherif M.; Abdalla, Yasser S.

doi:10.1016/j.aeue.2021.153882

Cited by 2 publications

(1 citation statement)

References 100 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the performance can be sustained due to the low threshold voltage transistor in the critical path. A high threshold voltage is applied to the sleep transistors based on the MTCMOS technique [11]- [13]. Therefore the sleep transistor turns off during standby mode.…”

Section: Comparator With Dtts and Mtscstackmentioning

confidence: 99%

A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques

Mustaffa

2021

IJRES

View full text Add to dashboard Cite

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.

show abstract

Section: Comparator With Dtts and Mtscstackmentioning

confidence: 99%