Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

Sharroush, Sherif M.; Abdalla, Yasser S.

doi:10.1016/j.vlsi.2024.102154

Integration

2024

DOI: 10.1016/j.vlsi.2024.102154

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Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

Sherif M. Sharroush,

Yasser S. Abdalla

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Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

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References 40 publications

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