Design and Optimization of 4-bit Absolute-value Detector Based on CMOS

Abstract

With the development of neural signal acquisition systems, spike-sorting algorithms have been paid full attention. As one of the most extensively used spike-detection algorithms, a 4-bit absolute-value detector is designed in the paper, which comprises three types of architecture. The first design is using combinational logic circuit through a truth table of the absolute value of 2′s complement format and a comparator; the second design is a combination of a series of half adders and transmission gates and a comparator; the third design consists of a combinational logic circuit by truth table of 2′s complement and a cascade of full adders. Then the paper compares the total number of stages and consuming transistors of each circuit, and finally chooses the second circuit, which has five stages and 74 transistors of consumption, as the object of following optimization of critical path delay and energy consumption. With gate sizing, the optimized critical path delay is about 43.05 tp0. The original energy consumption under minimum delay is 49.88C, and the optimized energy consumption under 1.5x minimum delay is 30.35C which is reduced by 39.16%. The processing of the functional realization and circuit optimization of absolute-value detectors can both benefit from the design presented in this work.

A methodology of designing and optimising a 4-bit absolute-value detector for the application of Brain-computer Interface

“…Carlson, Dewdney et al selected a half-adder in the transcoder module and combined CMOS and pass-transistor logic (PTL) to reduce the number of transistors [7]. Jia designed a combinational logic circuit for transcoding and applied full adders to the comparator module [8]. On this basis, Jia proposed the possibility of transcoding with the truth table.…”

4-bit absolute value detection for digital signal processing applications

“…The paper [12] first suggests three different topologies. The first topology makes use of a comparator, a truth table for the absolute value of the 2's complement format, and a combinational logic circuit.…”