Parallel testing of parametric faults in a three-dimensional dynamic random-access memory

Abstract

Ihis paper presents a testable design of dynamic randomaccess memory (DRAM) architecture which allows one to access multiple cells in a word l i e simultaneously. The technique utilizes the two-dimensional (2D) organization of the DRAM and the resulting speedup of the conventional algorithms is considerable. This paper specifically investigates the failure mechanisms in the three-dimensional (3D) DRAM with trench-type capacitor. As opposed to the earlier approaches for testing parametric faults that employed sliding diagonal-type tests with O (n 3 / 2) complexity, the algorithms discussed in this paper are different and have O (m) complexity, where p is the number of subarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test (BIST) applications.

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

“…This section derives the new Bit Line Imbalance Fault (BLIF) algorithm, which improves the fault coverage of the existing BLIF algorithm [5,6]. Before the improved version will be introduced, the BLIF will be described together with it's traditional algorithm.…”

“…Traditionally BILFs are tested by applying walking 1 using fast-row addressing direction [2,6]. In addition, most authors have solved the problem of detecting ADDFs by using a test called Moving Inversion 'MOVI' [4,7,8].…”

A BIST ram architecture with parallel testing in a microprogram rom

“…The 9-cell test patterns can detect the worst-case 9-cell neighborhood pattern-sensitive faults in parallel [3,5,8]. The following is the total test time of test procedure 2.…”

Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

“…This paper explores several of these failure modes and the consequent fault models and identifies parametric test procedures for these faults. General test procedures for RAM's were developed in the past [l], but they were found inadequate for testing newer silicon RAM's in two ways; they did not cover all classes of parametric faults and they wasted time on improbable faults [ 113, [25]. These problems led researchers to study the physical causes of silicon RAM failures to devise efficient new ways of testing these RAM's.…”

“…Dekker et al [ 111 studied faults in silicon SRAMs, based on the inductive fault analysis methods of [15], [32] and the realistic fault models of [22]. Mazumder [25] studied failure mechanisms in silicon DRAM'S and proposed efficient test algorithms based on the observed mechanisms.…”