Parallel logic simulation of VLSI systems

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

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“…There are several surveys on parallel logic simulation [4,19]. In particular, cycle-based simulation approaches are used by IBM and others [15].…”

Section: Related Workmentioning

confidence: 99%

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Şen

Akşanlı

Bozkurt

2011

Int J Parallel Prog

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“…Several partitioning algorithms are included in DVS: RANDOM [3], BFS(Breath-First-Search) [3], DFS(DepthFirst-Search) [3] and the design-driven partitioning algorithm.…”

Section: Dvs[16]: a Framework For Distributed Verilog[23] Simulationmentioning

confidence: 99%

A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation

Tropper

2007

21st International Workshop on Principles of Advanced and Distributed Simulation (PADS'07)

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Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance.Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

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“…Parallel simulation tools are frequently used to simulate large and complex digital circuits in order to reduce time for simulation [3]. To extract better performance from parallel logic simulators, partitioning techniques are necessary [5,19,20].…”

Section: Introductionmentioning

confidence: 99%