Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Abstract

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.

Optimising simulation data structures for the Xeon Phi

“…It is possible to directly compare the performance of our data structure with the result they report for only two of their circuits, working BLIF representations of the others not being available. Table II shows that when our data structure is run even on one core of a standard Intel i7, the performance substantially exceeds the results reported from [12], when we use the metric of nanoseconds per gate simulation.…”

“…In contrast to our work, Chatterjee, Deorio, and Bertacco [10], [2], [11], Sen, Aksanli, and Bozkurt [12], and [13], [14] use circuit partitioning algorithms to achieve fast simulation.…”

“…In [12], the authors use partitioning and replication in conjunction with levelization in order to handle the problem that the GPUs provide a small amount of shared memory.…”

Mu-GSIM: A mutation testing simulator on GPUs

“…Sen et al [14] also proposed a logic simulator by representing the circuit as an And-Inverter Graph. They have also used a form of partitioning for isolating a set of gates that are responsible for evaluating a particular set of primary outputs [15]. The second work of Bombieri et al [16] used OpenCL for accelerating simulation algorithms for designs written in SystemC.…”

Parallelization of Cycle-Based Logic Simulation

“…One way to accelerate the logic simulation of digital circuits is to exploit Graphics Processing Units (GPUs) and general purpose programming models such as Compute Unified Device Architecture (CUDA), [1,2], for the parallelization. Examples of parallel approaches to logic simulation have been proposed in [3,4,5,6,7,8,9,10,11]. Cycle-based simulation is considered in [3] and in [8].…”