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This paper presents a load balancing algorithm for a discrete event simulation executed under Time Warp.The algorithm rests upon recent developments in active process migration [l], which permit the use of dynamic strategies. Dynamic load balancing allows for readjustments when resource requirements vary during simulation. It is also useful when initial resource predictions are unknown or incorrect.A simulated multiprocessor environment (PARALLEX) was developed in order to evaluate the algorithm. Our results indicate that substantial performance gains may be realized with the algorithm.

Many partitioning algorithms have been proposed for distributed VLSI simulation. Typically, they make use of a gate level netlist, and attempt to achieve a minimal cut size subject to a load balance constraint. The algorithm executes on a hypergraph which represents the netlist. In this paper we propose a design-driven iterative partitioning algorithm for Verilog based on module instances instead of gates. We do this in order to take advantage of the design hierarchy information contained in the modules and their instances. A Verilog instance represents one vertex in the circuit hypergraph. The vertex can be flattened into multiple vertices in the event that a load balance is not achieved by instance based partitioning. In this case the algorithm flattens the largest instance and moves gates between the partitions in order to improve the load balance.Our experiments show that this partitioning algorithm produces a smaller cutsize than is produced by hmetis on a gate-level netlist. It produces better speedup for the simulation because it takes advantage of the design hierarchy.

We present, in this paper, a dynamic load balancing algorithm developed for Clustered Time W a r p , a hybrid appmach which makes iisc! of Time W a r p het.ween cliisters of LPs and a wqiieiitial mechanism within the clusters. The load balancing algorit.hm fociisw on distributing the load of the simidation evenly among the procestton and then tries to reduce interprocesmr commiinication... We make use of a t.riggering technique based on the throiighpiit of the simiilation system. The algorithm was implemented and its performance was measiired tisin two of the largest benchmark digital circuits of the 18CAS'89 series. In order to memiire the effects of the algorithm on workload distribution, inter-processor conimiinicat.ion and rollback, we defined three distinct metrics. bsidts show that by dynamically balancing the load, the throughput was improved by 40 to 100% when compared to Time Warp. Throughput. is t.he number of non mllf.nl-bact message events per unit time. When the algorithm tried to reduce inter-processor commiinication, rollback. were siihstantially rediiced. Severt.hdess, no srihstantial improvement was ohserved on the overall simiilation time, siig esting that load distribution is the most important &tor to he taken into consideration in speeding iip the simidihon of digital circuits.

There is a wide-spread usage of hardware design languages (HDL)

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