Parallel decoding architectures for low density parity check codes

Howland, C.; Blanksby, Andrew

doi:10.1109/iscas.2001.922344

Cited by 59 publications

(39 citation statements)

References 10 publications

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“…Howland and Blanskby [182] suggest two possible hardware architectures, namely a hardware-sharing and a parallel decoder architecture. After contrasting the two architectures, the authors opt for advocating the parallel 22 decoder architecture, mainly for the reasons of its lower power dissipation and the reduced amount amount of control logic required, as well as owing to the inherent suitability of the architecture for the SPA.…”

Section: E Hardware Implementation Of Low-density Parity-check Codesmentioning

confidence: 99%

Low-Density Parity-Check Codes and Their Rateless Relatives

Bonello

Chen

Hanzo

2011

IEEE Commun. Surv. Tutorials

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Section: E Hardware Implementation Of Low-density Parity-check Codesmentioning

confidence: 99%

Low-Density Parity-Check Codes and Their Rateless Relatives

Bonello

Chen

Hanzo

2011

IEEE Commun. Surv. Tutorials

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“…In [12], the network has a delay of 15.4 ns and an average interconnect length of 3 mm, and occupies 50% of the 52.5 mm overall area, constituting a performance and area bottleneck that renders practical LDPC decoders of codes longer than 1024 more difficult to implement.…”

Section: E Bi-directional Networkmentioning

confidence: 99%

“…The combination of the TDMP algorithm and architecture with the AA-structure of the code eliminates the interconnect bottleneck of existing parallel architectures [12] that complicates practical decoder implementations of long LDPC codes. In particular, the chip presented here occupies an area 3.7 times smaller, and decodes LDPC codes twice the length (resulting in higher coding gain) compared to the chip presented in [12].…”

Section: F Chip Characteristicsmentioning

confidence: 99%

“…Contemporary LDPC decoders are based on a parallel or serialized version of the TPMP algorithm. The complexity of a fully parallel decoder [12] grows linearly with the block length and is practical only for relatively short LDPC codes, while a serial decoder [13] algorithmic performance by increasing the block length, and is primarily targeted for low-throughput applications.…”

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confidence: 99%

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A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

Mansour

Shanbhag

2006

IEEE J. Solid-State Circuits

171

105

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Abstract-A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.

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“…In a fully parallel decoder, each individual variable node or check node is physically implemented as a node decoding unit, and all the units are connected through an interconnection network reflecting the bipartite graph connectivity. It is clear that such fully parallel decoders can achieve very high decoding throughput, e.g., Howland and Blanksby [9] [10] have implemented a 1Gbps decoder for 1024-bit, rate 1/2 LDPC code. However, the fully parallel decoders suffers from high implementation complexity, especially the prohibitive routing wire overhead with too many global long routing wires.…”

Section: Ldpc Decoder Implementation Issuesmentioning

confidence: 99%

Design of VLSI implementation-oriented LDPC codes

Zhong

Zhang

2003

2003 IEEE 58th Vehicular Technology Conference. VTC 2003-Fall (IEEE Cat. No.03CH37484)

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Abstract-Recently, low-density parity-check (LDPC) codes have attracted much attention because of their excellent errorcorrecting performance and highly parallelizable decoding scheme. However, the effective VLSI implementation of an LDPC decoder remains a big challenge and is a crucial issue in determining how well we can exploit the benefits of the LDPC codes in the real applications. In this paper, following the joint code and decoder design philosophy, we propose a semirandom design scheme to construct the LDPC codes that not only exhibit very good error-correcting performance but also effectively fit to partially parallel VLSI decoder implementations. The corresponding partially parallel decoder has a very regular structure and simple control mechanism. Our computer simulations show that such LDPC codes achieve very good performance comparable to their counterparts constructed in a fully random scheme, which however have little chance of fitting to partially parallel decoder implementations.

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Parallel decoding architectures for low density parity check codes

Cited by 59 publications

References 10 publications

Low-Density Parity-Check Codes and Their Rateless Relatives

Low-Density Parity-Check Codes and Their Rateless Relatives

A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

Design of VLSI implementation-oriented LDPC codes

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