ParaLaR: A parallel FPGA router based on Lagrangian relaxation

Hoo, Chin Hau; Kumar, Akash; Ha, Yajun

doi:10.1109/fpl.2015.7294012

Cited by 8 publications

(16 citation statements)

References 16 publications

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“…Most parallel FPGA routers parallelize PathFinder, often with modifications to ensure determinism or to optimize performance [11], [4], [12], [13], [14], [15]. Alternatives include linear programming with Lagrangian relaxation [16] and using Bellman-Ford in lieu of Maze Expansion, which is amenable to parallelization using a GPU [17]; although both of these papers achieve substantial speedups compared to a single-threaded CPU, they also report significantly degraded solution quality.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Moctar

Stojilović

Brisk

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallelization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84× and 3.67×, respectively, compared to VPR's singlethreaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67× and 5.46×, while sacrificing the guarantee of reproducible results.

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Section: Related Workmentioning

confidence: 99%

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Moctar

Stojilović

Brisk

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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“…One of the first attempts in parallelizing this routing process was done in [4]. Here, the authors formulated the problem as a Binary Integer Linear Program (BILP), applied the Lagrange relaxation to eliminate constraints, and then solved the resulting optimization problem using the sub-gradient method and a Steiner tree algorithm.…”

Section: Introductionmentioning

confidence: 99%

“…The routing problem in FPGA or a electronic circuit is formulated as a weighted grid graph G(V , E), where V and E are the sets of certain vertices and edges, respectively, and there is a cost associated with each edge [4], [6]. In this grid graph, we have three types of vertices; the net vertices, a Steiner vertices, and the other vertices.…”

Section: Introductionmentioning

confidence: 99%

“…Here, the goal is to find a route for each net such that the union of all the routes will minimize the total path cost of the graph G, which is directly proportional to the total wire length of FPGA. To achieve this objective, the problem of routing of nets is formulated as an LP problem given by [4] (ParaLaR paper). min…”

Section: Introductionmentioning

confidence: 99%

“…This introduces Lagrange multipliers λ e for each constraint, with relaxation carried out by adding λ e times the corresponding constraint to the objective function. That is, instead of the LP given in ( 1)-(2c), we have the following [4]…”

Section: Introductionmentioning

confidence: 99%

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Parallel FPGA Routers With Lagrange Relaxation

Agrawal,

Ahuja,

Maheshwari

et al. 2023

IEEE Access

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Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD). These algorithms formulate the routing process as a Linear Program (LP) and solve it using the Lagrange relaxation, an adapted sub-gradient method, and a Steiner tree algorithm. When tested on the MCNC benchmark circuits, using underlying VPR 7.0 for packing and placement, ParaLaR and ParaLarPD both outperformed VPR 7.0 for routing, with ParaLarPD being better. We have three main contributions here. Recently, in 2020, a new variant of VPR, i.e. VPR 8.0, has been proposed. Hence, first, we make ParaLarPD compatible for testing on MCNC benchmark circuits using VPR 8.0. Second, we adapt ParaLarPD for the larger benchmark circuits than MCNC, i.e., VTR, using both VPR 7.0 and VPR 8.0, and perform thorough evaluation. Finally, and third, we improve ParaLarPD further. We design a family of Lagrange heuristics that better the Lagrange relaxation process of ParaLarPD. We term our new algorithm ParaLarH and test it on both the benchmark circuits (MCNC and VTR) and using both the VPRs (VPR 7.0 and VPR 8.0). When tested on MCNC and VTR benchmark circuits, VPR (VPR 7.0 and VPR 8.0) is outperformed by both ParaLarH and ParaLarPD, with average gains given below. The minimum channel width improvements are 22% and 12%, respectively. The total wire length improvements for both are 45%. Finally, the average critical path delay improvements for both are almost the same (37% and 35%, respectively).INDEX TERMS FPGA, lagrangian heuristics, LP, optimization, subgradient methods. * Besides being a routing algorithm, VPR is also used to pack and place before other routing algorithms are applied

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ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding

Hoo

Kumar

2017

2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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ParaLaR: A parallel FPGA router based on Lagrangian relaxation

Cited by 8 publications

References 16 publications

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Parallel FPGA Routers With Lagrange Relaxation

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding

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