ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding

Hoo, Chin Hau; Kumar, Akash

doi:10.1109/fccm.2017.34

Cited by 13 publications

(2 citation statements)

References 12 publications

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“…Although FPGA speed and capacity have increased under Moore's Law, there has been no increase in design productivity, creating a large gap between the Open Access Library Journal ability of FPGAs and the ability to use them effectively. This gap increases the cost of market development time for FPGA-based designs, with insufficient design tools being one of the main factors [2]. In my research, I applied the fitness function calculation to the parallel genetic algorithm (PGA) to take advantage of the high speed of FPGA.…”

Section: Introductionmentioning

confidence: 99%

A Prototype of FPGA Based on Genetic Algorithm Core Connected to a Cluster

Alwzan¹,

Khidhir²,

Thabit³

2020

OALib

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In this paper, it was proposed to design and implement a system of parallel processing to find the required solutions from selective algorithms as quickly. Motives for writing paper are the current performance of computer systems that depend on evolutionary algorithms (EA), and the wide spread of the (EA), and its application to a very wide range of scientific fields, and by taking advantage of the Field programmable gate array (FPGA) board due to its high speed of implementation. The values were validated and the Genetic Algorithm (GA) was used as a functional model and implementation. Also, in the most important stages, the process of calculating fitness function, which is considered an executive criterion for the (GA), with terminal computers with high speeds and medium specifications, was done for the purposes of calculating fitness function independently of Board. Identical results were obtained at 100% accuracy by applying the work to a non-linear quadratic.

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Section: Introductionmentioning

confidence: 99%

A Prototype of FPGA Based on Genetic Algorithm Core Connected to a Cluster

Alwzan¹,

Khidhir²,

Thabit³

2020

OALib

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“…Many attempts have been employed to speed-up the routing process [2]- [10]. Some of them use algorithmic improvements and new techniques to speed up routing [2]- [7], while others rely on a multithreaded approach [7]- [10]. Improving the total wire-length and maximum clock frequency is difficult to obtain.…”

Section: Introductionmentioning

confidence: 99%

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

Vercruyce

Vansteenkiste

Stroobandt

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGA routing is an important part of physical design as the programmable interconnection network requires the majority of the total silicon area and the connections largely contribute to delay and power. It should also occur with minimum runtime to enable efficient design exploration. In this work we elaborate on the concept of the connection-based routing principle. The algorithm is improved and a timing-driven version is introduced. The router, called CROUTE, is implemented in an easy to adapt FPGA CAD framework written in Java, which is publicly available on GitHub. Quality and runtime are compared to the state-of-the-art router in VPR 7.0.7. Benchmarking is done with the TITAN23 design suite, which consists of large heterogeneous designs targeted to a detailed representation of the Stratix IV FPGA. CROUTE gains in both the total wirelength and maximum clock frequency while reducing the routing runtime. The total wire-length reduces by 11% and the maximum clock frequency increases by 6%. These high-quality results are obtained in 3.4x less routing runtime.

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Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Moctar

Stojilović

Brisk

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallelization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84× and 3.67×, respectively, compared to VPR's singlethreaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67× and 5.46×, while sacrificing the guarantee of reproducible results.

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ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding

Cited by 13 publications

References 12 publications

A Prototype of FPGA Based on Genetic Algorithm Core Connected to a Cluster

A Prototype of FPGA Based on Genetic Algorithm Core Connected to a Cluster

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

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