Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Moctar, Yehdhih Ould Mohammed; Stojilović, Mirjana; Brisk, Philip

doi:10.1109/fpl.2018.00011

Cited by 10 publications

(8 citation statements)

References 18 publications

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“…The architecture parameters used for our experiments are given in Table 1, which are most commonly used [12,13,23]. In Table 1, the values of N and K specify that the CLBs in the architecture contained ten fracturable logic elements (FLEs) and each FLE had six inputs, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…There is no general rule of choosing the initial value of the channel width for experimental purposes. However, a value of 20% to 40% more than the minimum channel width obtained from VPR is commonly used [6,23]. For our experiments, both ParaLarPD and ParaLaR are initialized with initial channel width (W) as 1.2W min , where W min is the minimum channel width obtained from VPR.…”

Section: Resultsmentioning

confidence: 99%

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ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

et al. 2019

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In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing process to achieve significant speed-ups (the resulting algorithm is termed as ParaLaR). However, this approach has certain weaknesses. Namely, the constraints violation by the solution and a standard routing metric could be improved. We address these two issues here. In this paper, we use the LP framework of ParaLaR and solve it using the primal-dual sub-gradient method that better exploits the problem properties. We also propose a better way to update the size of the step taken by this iterative algorithm. We call our algorithm as ParaLarPD. We perform experiments on a set of standard benchmarks, where we show that our algorithm outperforms not just ParaLaR but the standard existing algorithm VPR as well. We perform experiments with two different configurations. We achieve 20% average improvement in the constraints violation and the standard metric of the minimum channel width (both of which are related) when compared with ParaLaR. When compared to VPR, we get average improvements of 28% in the minimum channel width (there is no constraints violation in VPR). We obtain the same value for the total wire length as by ParaLaR, which is 49% better on an average than that obtained by VPR. This is the original metric to be minimized, for which ParaLaR was proposed. Next, we look at the third and easily measurable metric of critical path delay. On an average, ParaLarPD gives 2% larger critical path delay than ParaLaR and 3% better than VPR. We achieve maximum relative speed-ups of up to seven times when running a parallel version of our algorithm using eight threads as compared to the sequential implementation. These speed-ups are similar to those as obtained by ParaLaR.CAD (computer-aided design) tools. This can be achieved in two ways. First, by parallelizing the routing algorithms for hardware having multiple cores. However, the pathfinder algorithm [3], which is one of the most commonly used FPGA routing algorithm is intrinsically sequential. Hence, this approach seems inappropriate for parallelizing all types of FPGA routing algorithms.Second, instead of compiling the entire design together, the users can partition their design, compile partitions progressively, and then assemble all the partitions to form the entire design. Some existing works have proposed this approach [4,5]. However, the routing resources required by one partition may be held by another partition, i.e., there is no guarantee to have balanced partitions. In other words, in this approach, there is a need to tackle the difficulties arising in sharing of routing resources.The authors in ParaLaR [6] overcome the limitations of existing approaches by formulating the FPGA routing problem as an optimization problem [7]. Here, the objective function is linear an...

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

et al. 2019

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“…We use the most common architecture parameters [2,4,5,23] as given in Table 2. Here, the value of N specifies that the CLBs in the architecture contains ten Fracturable Logic Elements (FLEs).…”

Section: Setupmentioning

confidence: 99%

“…There is no general rule of choosing the initial value of the channel width for experimental purposes. However, a value of 20% to 40% more than the minimum channel width obtained from VPR is commonly used [3,4,23]. Our algorithms are initialized with the initial channel width (W ) as 1.2W min , where W min is the minimum channel width obtained from VPR.…”

Section: Setupmentioning

confidence: 99%

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

Agrawal,

Ahuja,

Maheshwari

et al. 2020

Preprint

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Routing of the nets in Field Programmable Gate Array (FPGA) design flow is one of the most time consuming steps. Although Versatile Place and Route (VPR), which is a commonly used algorithm for this purpose, routes effectively, it is slow in execution. One way to accelerate this design flow is to use parallelization. Since VPR is intrinsically sequential, a set of parallel algorithms have been recently proposed for this purpose (ParaLaR and ParaLarPD).These algorithms formulate the routing process as a Linear Program (LP) and solve it using the Lagrange relaxation, the sub-gradient method, and the Steiner tree algorithm. Out of the many metrics available to check the effectiveness of routing, ParaLarPD, which is an improved version of ParaLaR, suffers from large violations in the constraints of the LP problem (which is related to the minimum channel width metric) as well as an easily measurable critical path delay metric that can be improved further.In this paper, we introduce a set of novel Lagrange heuristics that improve the Lagrange relaxation process. When tested on the MCNC benchmark circuits, on an average, this leads to halving of the constraints violation, up to 10% improvement in the minimum channel width, and up to 8% reduction in the critical path delay as obtained from ParaLarPD. We term our new algorithm as ParaLarH. Due to the increased work in the Lagrange relaxation process, as compared to ParaLarPD, ParaLarH does slightly deteriorate the speedup obtained because of parallelization, however, this aspect is easily compensated by using more number of threads.

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“…The arrival and required times are calculated in a forward and backward traversal of the timing graph respectively. slack = Treq − Tarr − T del (9) The forward traversal calculates the arrival time of all nodes in the timing graph and gives us the maximum delay in the circuit (D max ). This maximum delay is set as the required time of the timing path leaf nodes in the backward traversal.…”

Section: Timing-driven Connection Routermentioning

confidence: 99%

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

Vercruyce

Vansteenkiste

Stroobandt

2019

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGA routing is an important part of physical design as the programmable interconnection network requires the majority of the total silicon area and the connections largely contribute to delay and power. It should also occur with minimum runtime to enable efficient design exploration. In this work we elaborate on the concept of the connection-based routing principle. The algorithm is improved and a timing-driven version is introduced. The router, called CROUTE, is implemented in an easy to adapt FPGA CAD framework written in Java, which is publicly available on GitHub. Quality and runtime are compared to the state-of-the-art router in VPR 7.0.7. Benchmarking is done with the TITAN23 design suite, which consists of large heterogeneous designs targeted to a detailed representation of the Stratix IV FPGA. CROUTE gains in both the total wirelength and maximum clock frequency while reducing the routing runtime. The total wire-length reduces by 11% and the maximum clock frequency increases by 6%. These high-quality results are obtained in 3.4x less routing runtime.

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Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model

Cited by 10 publications

References 18 publications

ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

ParaLarH: Parallel FPGA Router based upon Lagrange Heuristics

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router

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