PAM programming environments: practice and experience

Bertin, Patrice; Touati, H.

doi:10.1109/fpga.1994.315599

Cited by 43 publications

(13 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Integrating Reconfigurable computing with traditional Computing systems has been a challenge since the early days of FPGAs; several machines have been designed to this direction, such as PAM [1], Splash [2], and DISC [3]. The primary drawback of all these attempts was the limited bandwidth and increased communication latency between the host general purpose processor and the reconfigurable device.…”

Section: List Of Tablesmentioning

confidence: 99%

General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. n this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. Laboratory: Computer Engineering Codenumber : CE-MS

show abstract

Section: List Of Tablesmentioning

confidence: 99%

General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

View full text Add to dashboard Cite

show abstract

“…Each application has specific functions that are loaded when the FPGA is started. Some examples of CTR systems are SPLASH [9] and PAM [10]. For run-time reconfiguration (RTR), the FPGA changes configuration while it is operating.…”

Section: Background and Related Workmentioning

confidence: 99%

Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

2002

View full text Add to dashboard Cite

This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. By enabling multiple applications to be dynamically loaded into a single hardware device, the DHP architecture provides a scalable mechanism for implementing high-performance programmable routers. The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. Implementation options are described as well as the prototype testbed at Washington University in Saint Louis which utilizes the partial reconfiguration capability of modern field programmable gate arrays. Ó 2002 Published by Elsevier Science B.V.

show abstract

“…The following will discuss only FPGA-related work. PamDC [2,10] was one of the first FPGA-related tools to be based on a general purpose language (C++) that programmatically generated circuits. It was developed for use with DecPerle-1 and was used successfully on a large set of applications.…”

Section: Applicationsmentioning

confidence: 99%