Dynamic hardware plugins: exploiting reconfigurable hardware for high-performance programmable routers

Abstract

This paper presents the dynamic hardware plugins (DHP) architecture for implementing multiple networking applications in hardware at programmable routers. By enabling multiple applications to be dynamically loaded into a single hardware device, the DHP architecture provides a scalable mechanism for implementing high-performance programmable routers. The DHP architecture is presented within the context of a programmable router architecture which processes flows in both software and hardware. Implementation options are described as well as the prototype testbed at Washington University in Saint Louis which utilizes the partial reconfiguration capability of modern field programmable gate arrays. Ó 2002 Published by Elsevier Science B.V.

Design of a network service processing platform for data path customization

“…The packet processing systems of programmable routers are typically implemented using network processors [21,25], with a number of commercial network processors being available from Intel, AMCC, EZchip, etc. Programmability in network systems has also been proposed on the basis of programmable logic devices [9,22].…”

“…Such modules have been proposed for Click [12] and NP-Click [19] as well as for router plugins [3] and hardware plugins [22]. Our network service architecture [6] uses a similarly structured approach, where services usually implement full network functionalities or protocols, which represent self-contained network processing and protocol operations.…”

Service-Centric End-to-End Abstractions in Next-Generation Networks

“…These embedded multiprocessors employ parallel processor cores to achieve Gigabit per second link speeds for header-processing applications and tens to hundreds of Megabit per second link speeds for payload-processing applications [22]. A third choice is to use programmable logic devices (e.g., FPGAs) to implement some of packet forwarding and processing tasks [23].…”

Design considerations for network processor operating systems

“…The need for a specialized architecture is due to the uniqueness of the workload of NPs, which is dominated by many small tasks and high-bandwidth I/O operations [21]. Another alternative for implementing packet processing functions is programmable logic devices, e.g., field-programmable gate arrays (FPGAs), which are more suitable for some of the data flow style processing functions [1,18]. The design considerations for run-time support in FPGA-based systems are very similar to those of conventional NPs and thus the results of our work can be expected to be equally applicable to this domain.…”