A CAD Suite for High-Performance FPGA Design

Hutchings, Brad; Bellows, Peter; Hawkins, Joseph A.; Hemmert, Scott; Nelson, Brent; Rytting, Mike

doi:10.21236/ada450475

Cited by 22 publications

(16 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As a concrete instantiation of an open CAD framework the JHDL system [11,12] was created. The term JHDL can be used to refer both to the JHDL circuit design language itself as well as to the associated JHDL open CAD framework.…”

Section: An Instance Of An Open Cad Framework For Configurable Computmentioning

confidence: 99%

See 1 more Smart Citation

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Nelson

Hutchings

Wirthlin

2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

Configurable Computing Machines (CCMs) are computing machines based on reconfigurable circuit technology such as field programmable gate-arrays. Early researchers recognized CCMs as a new, flexible, and powerful class of computer. The earliest CCMs featured rudimentary but significant integrated design, debug, and deployment (runtime) environments. This paper reviews those environments and the contributions they made and considers the progress made over the past 20 years in providing support for the "3 D's" of configurable computing application development: design, debug, and deployment. It then introduces an integrated CAD framework for the creation of CCM CAD tools and describes a series of experiments in creating such a CAD tool suite -the JHDL system. The paper reviews lessons learned from that work and concludes by discussing the role integrated design, debug, and runtime environments will play in future CCM-based systems.

show abstract

Section: An Instance Of An Open Cad Framework For Configurable Computmentioning

confidence: 99%

“…1. The JHDL circuit design language has been amply documented elsewhere [12][13][14] (http://www.jhdl.org) and so will not be discussed more in detail here.…”

Section: An Instance Of An Open Cad Framework For Configurable Computmentioning

confidence: 99%

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Nelson

Hutchings

Wirthlin

2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

show abstract

“…Therefore the verification of a run-time reconfigurable system is difficult since the designer must evaluate the system on actual hardware. One design tool that considers simulation of run-time reconfigurable systems is JHDL [59,60]. JHDL is a design tool that allows simulation of a runtime reconfigurable design without implementing it on actual hardware.…”

Section: • Lic (Loosely Coupled With An Integrated Cpu)mentioning

confidence: 99%

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Shoa

Shirani

2005

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.

show abstract

“…SLAAC hardware was used as the pilot platform for development of the JHDL tool suite, which has been extensively documented in other publications [3,5]. JHDL uses the "readback" feature of modern FPGAs to extract the complete state of the circuit from executing hardware.…”

Section: Acceleration For Advanced Debuggingmentioning

confidence: 99%

“…Finally, the co-simulation techniques discussed in Section 5 are similar to the capabilities of the JHDL tools [5]. The key contribution of the co-simulator is the ability to precisely simulate real-world hardware-software interactions down to the register-transfer level of the device driver, using unmodified driver code.…”

Section: Related Workmentioning

confidence: 99%

High-Visibility Debug-By-Design for FPGA Platforms

Bellows¹

2005

J Supercomput

Self Cite

View full text Add to dashboard Cite

The true measure of a general-purpose FPGA platform is user design productivity, not just raw hardware performance. User productivity is a function of several interdependent components of the design environment: system firmware, simulation models, debugging support, device drivers, APIs and so forth. The careful, coordinated design of these components determines the level of debugging visibility and, ultimately, the ease of development for the end user. This paper examines the innovative aspects of the development of the SLAAC FPGA platforms and programming environment. Several novel techniques are presented, including circuit designs for transparent clock stepping and host access to on-board memories; device driver strategies and a "register compiler" to ease the design and testing of the hardware-software interface; and a co-simulation approach for advanced debugging of firmware, device drivers and user applications.

show abstract

A CAD Suite for High-Performance FPGA Design

Cited by 22 publications

References 9 publications

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

High-Visibility Debug-By-Design for FPGA Platforms

Contact Info

Product

Resources

About