Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

Kim, Sukpil; Kim, Wonjoo; Hyun, Jaewoong; Byun, Seung-Woo; Koo, Junemp; Lee, Junghoon; Cho, Kyounglae; Lim, Soon Kwon; Park, Jongbong; Yoo, In-Kyeong; Lee, Choong-Ho; Park, Donggun; Park, Yoondong

doi:10.1109/vlsit.2006.1705228

Cited by 22 publications

(11 citation statements)

References 2 publications

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“…Moreover, threshold voltage (V t ) variability in the FinFETs and TG devices is much smaller than that in the conventional bulk planar MOSFETs because the random dopant fluctuation (RDF) induced V t variation is negligible in the FinFETs and TG devices due to the undoped fin-channels [14][15][16][17][18][19][20][21][22]. Therefore, the scaled charge trapping (CT) type fin-channel flash memories using silicon on insulator (SOI)-based fin-channels and body-tied bulk Si fin-channels have actively been developed [23][24][25][26][27][28][29][30][31][32]. However, a high-k blocking layer is strongly required in the ultimately scaled CT type flash memory fabrication to overcome the gate coupling area decrease with scaling down the device size [33].…”

Section: Introductionmentioning

confidence: 99%

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Liu

Nabatame

Matsukawa

et al. 2014

JLPEA

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The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al 2 O 3 and SiO 2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V t ) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al 2 O 3 blocking layer instead of a SiO 2 blocking layer. It was also confirmed that the variability of V t before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. . Low Power Electron. Appl. 2014, 4 154 OPEN ACCESS J

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Section: Introductionmentioning

confidence: 99%

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Liu

Nabatame

Matsukawa

et al. 2014

JLPEA

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“…[13][14][15][16][17][18][19] Therefore, scaled fin-channel flash memory cell transistors using siliconon-insulator (SOI)-based and body-tied bulk silicon (Si) fin channels have been actively developed, and the scalability of fin-channel flash memories down to a gate length (L g ) of 20 nm has been demonstrated. [20][21][22][23][24][25][26][27][28][29] However, the gate material dependence of the electrical characteristics of SOIbased FinFET flash memories has not been investigated sufficiently. Very recently, we have developed floating-gate (FG)-type crystalline-Si and polycrystalline-Si (poly-Si) finchannel flash memories with TG and DG structures, and confirmed that the TG structure has a larger memory window and a higher SCE immunity than the DG structure owing to the additional top gate and recessed buried oxide (BOX) region, which strengthen the controllability of the channel potential and increase the coupling ratio of the FG to the control gate (CG).…”

Section: Introductionmentioning

confidence: 99%

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

Liu¹,

Matsukawa²,

Endo³

et al. 2014

Jpn. J. Appl. Phys.

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Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (V t) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal–oxide–nitride–oxide–silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si–oxide–nitride–oxide–silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial V t roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (L g) is scaled down to 46 nm or less.

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“…[15][16][17][18] Hence, the scaled 3D flash memory cell transistors formed using silicon-on-insulator (SOI)-based fin-channels, bodytied bulk silicon (Si) fin-channels, and vertical Si pillar channels have been actively developed and the scalability of fin-channel flash memories with the gate length down to 20 nm has been demostrated. [19][20][21][22][23][24][25][26][27][28][29][30] In such scaled flash memories, one of the most important issues is the reduction of operating voltage. However, in the conventional bulk planar MOSFET-type flash memory, it is very difficult to reduce the operating voltage because of the thick tunnel oxide and the thick interpoly dielectric (IPD) layers.…”

Section: Introductionmentioning

confidence: 99%

Experimental Study of Floating-Gate-Type Metal–Oxide–Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

Liu¹,

Guo²,

Kamei³

et al. 2012

Jpn. J. Appl. Phys.

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Mirage mediation reduces the fine-tuning in the minimal supersymmetric standard model by dynamically arranging a cancellation between anomaly-mediated and modulus-mediated supersymmetry breaking. We explore the conditions under which a mirage "messenger scale" is generated near the weak scale and the little hierarchy problem is solved. We do this by explicitly including the dynamics of the SUSY-breaking sector needed to cancel the cosmological constant. The most plausible scenario for generating a low mirage scale does not readily admit an extra-dimensional interpretation. We also review the possibilities for solving the µ/Bµ problem in such theories, a potential hidden source of fine-tuning.Keywords: Supersymmetry Breaking, Supersymmetric Standard Model, Supergravity Models. model (MSSM) is realized in nature has been eroded by the so-called "little hierarchy problem". In the MSSM, the little hierarchy appears as a tension between the two different roles played by the stop squark: on the one hand, the stop should be light to cut off the quadratic divergence in the Higgs boson (mass) 2 and thus minimize fine-tuning; on the other hand, the stop should be heavy enough to generate a physical mass for the Higgs boson above the LEP II bounds. This tension is exacerbated by renormalization group (RG) flow which tends to drive colored particles heavier than electroweak particles. The LEP II bound on charginos, along with the assumption of universal gaugino masses, generically ensures that the stop is quite heavy, requiring fine-tuning at the percent level to achieve successful electroweak symmetry breaking.One potential way to reduce the level of fine-tuning is to have a compressed SUSY spectrum at low scales. Any mechanism yielding such a spectrum while simultaneously evading the bound on the Higgs boson mass merits study. Mirage mediation [1, 2], based on the investigations of [3,4], claims to be such a mechanism. In mirage mediation, a cancellation between modulus mediation [5, 6] and anomaly mediation [7, 8] creates a distinctive low energy SUSY spectrum that appears to unify at a mirage "messenger scale" M mess M GUT . Because this cancellation occurs at every RG scale, there is no hidden fine-tuning between the modulus-and anomaly-mediated contributions [9]. In addition, mirage mediation generically yields large trilinear A terms which generate a large enough physical Higgs mass. Since the leading correction to the Higgs (mass) 2 goes like ∆m 2 Hu = − 3y 2 t 4π 2 m 2 t ln M mess mt , (1.1) the level of fine-tuning can be reduced if M mess is close to the weak scale.

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Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

Cited by 22 publications

References 2 publications

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

Experimental Study of Floating-Gate-Type Metal–Oxide–Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

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