Experimental Study of Floating-Gate-Type Metal–Oxide–Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

Abstract

Mirage mediation reduces the fine-tuning in the minimal supersymmetric standard model by dynamically arranging a cancellation between anomaly-mediated and modulus-mediated supersymmetry breaking. We explore the conditions under which a mirage "messenger scale" is generated near the weak scale and the little hierarchy problem is solved. We do this by explicitly including the dynamics of the SUSY-breaking sector needed to cancel the cosmological constant. The most plausible scenario for generating a low mirage scale does not readily admit an extra-dimensional interpretation. We also review the possibilities for solving the µ/Bµ problem in such theories, a potential hidden source of fine-tuning.Keywords: Supersymmetry Breaking, Supersymmetric Standard Model, Supergravity Models. model (MSSM) is realized in nature has been eroded by the so-called "little hierarchy problem". In the MSSM, the little hierarchy appears as a tension between the two different roles played by the stop squark: on the one hand, the stop should be light to cut off the quadratic divergence in the Higgs boson (mass) 2 and thus minimize fine-tuning; on the other hand, the stop should be heavy enough to generate a physical mass for the Higgs boson above the LEP II bounds. This tension is exacerbated by renormalization group (RG) flow which tends to drive colored particles heavier than electroweak particles. The LEP II bound on charginos, along with the assumption of universal gaugino masses, generically ensures that the stop is quite heavy, requiring fine-tuning at the percent level to achieve successful electroweak symmetry breaking.One potential way to reduce the level of fine-tuning is to have a compressed SUSY spectrum at low scales. Any mechanism yielding such a spectrum while simultaneously evading the bound on the Higgs boson mass merits study. Mirage mediation [1, 2], based on the investigations of [3,4], claims to be such a mechanism. In mirage mediation, a cancellation between modulus mediation [5, 6] and anomaly mediation [7, 8] creates a distinctive low energy SUSY spectrum that appears to unify at a mirage "messenger scale" M mess M GUT . Because this cancellation occurs at every RG scale, there is no hidden fine-tuning between the modulus-and anomaly-mediated contributions [9]. In addition, mirage mediation generically yields large trilinear A terms which generate a large enough physical Higgs mass. Since the leading correction to the Higgs (mass) 2 goes like ∆m 2 Hu = − 3y 2 t 4π 2 m 2 t ln M mess mt , (1.1) the level of fine-tuning can be reduced if M mess is close to the weak scale.

(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

“…Recently, we have developed FG-type and chargetrapping (CT)-type SOI-FinFET flash memories, and confirmed that the TG structure has a larger memory window and a higher SCE immunity than the DG structure owing to the additional top gate and recessed buried oxide (BOX) region (21)(22)(23)(24). Moreover, we have also demonstrated FG-type split-gate SOI-FinFET flash memories with highly suppressed overerase and experimentally confirmed that nanosize triangular cross-sectional tunnel areas are useful for the fabrication of low-operating-voltage flash memories (25,26). However, the fin channel shape and interpoly dielectric (IPD) material effects on the electrical characteristics of FG-type SOI-FinFET flash memories have not been investigated sufficiently, although the high-k dielectric stacks and barrier-engineered multilayers have been used as an IPD layer for improving the gate coupling of the conventional bulk planar FG-type flash memories (27)(28)(29)(30).…”

“…Note that this RIE process was accompanied by the etching of the BOX region, i.e., the recessed BOX region was automatically formed. Then, an 8-nm-thick tunnel oxide (T ox ) layer was formed by thermal oxidation at 850 o C, followed by the deposition of a 30-nm-thick n + -polycrystalline silicon (n + -poly-Si) layer as the FG material by low-pressure chemical vapor deposition (LPCVD) at 580 o C. After the FG formation by EB lithography and RIE, a 3-nm-thick thermal SiO 2 layer was formed on the FG surface by rapid thermal oxidation (RTO) at 950 o C for 80 s (26). Then, a 5-nm-thick nitride (Si 3 N 4 ) layer was deposited by LPCVD at 790 o C for all the sample wafers.…”

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

“…However, the blocking layer material effect on the electrical characteristics of SOI-FinFET flash memories has not been studied sufficiently. Very recently, we have demonstrated floating gate (FG) type split-gate fin-channel flash memories with a highly suppressed over erase, and experimentally confirmed that nanosize triangular cross-section tunnel areas are useful for the fabrication of the low operating voltage flash memories owing to the enhanced local electric field at the tips of triangular tunnel areas [35][36][37][38]. We have also fabricated and investigated FG type crystalline and polycrystalline Si fin-channel flash memories with DG and TG structures, and confirmed that TG structured flash memory shows the better SCE immunity and a larger memory window than the DG structured one owing to the additional top gate and recessed buried oxide (BOX) region [39][40][41].…”

Gate Structure Dependence of Variability in Polycrystalline Silicon Fin-Channel Flash Memories

“…31) For this reason, very recently, we have developed FG-type crystalline-Si fin-channel flash memories and demonstrated a splitgate fin-channel flash memory with highly suppressed overerase. [32][33][34][35][36][37] As further study, in this work, we fabricate scaled poly-Si fin-channel DG-and TG-type flash memories with a thin n þ -poly-Si FG, and systematically investigate the gate structure dependence of variability including V t and the S-slope before and after one P/E cycle.…”