p-type Channel Field-Effect Transistors

III–V compound semiconductor transistors—from planar to nanowire structures

“…A second problem is that a high-performance p -channel device, as required in CMOS, will have to be based on semiconductors with high hole mobility, such as Ge 14 , 74 or InGaSb. 75 Both have different relaxed lattice constants from InAs-rich InGaAs, which renders the combined integration on Si a very diffi cult technological problem. Several integration schemes are being pursued, such as direct wafer bonding, 76 , 77 epitaxial layer transfer to a silicon on insulator substrate, 78 and aspect ratio trapping (ART).…”

Heteroepitaxy of La2O3 and La2–xYxO3 on GaAs (111)A by Atomic Layer Deposition: Achieving Low Interface Trap Density

“…However, GaAs MOS devices suffer from Fermi-level pinning, which is mainly due to the high trap density of states at the oxide/GaAs interface. 1,2 In this work, we present a new way of passivating the interface trap states by growing an epitaxial layer of high-k dielectric oxide, La 2-x Y x O 3 , on GaAs(111)A, which effectively reduces the trap density and minimizes the frequency dispersion of capacitance.…”

Chemical Composition of Native Oxide Layers on In+Implanted and Thermally Annealed GaAs

“…This eect can be explained by the fact that arsenic atoms leave the surface layers during thermal annealing. The same eect was described in [12], where the XPS data measured for GaAs indicate the removal of As 2 O 3 oxide after annealing at above 500 The thicknesses of the native oxide layers were determined using the RBS/NR method. Four spectra for energies of the α particles between 3.035 and 3.060 MeV have been collected, for each studied sample.…”