P-186L:Late-News Poster: Development and Characteristic Analysis of Crystalline IGZO

Abstract

Crystalline indium gallium zinc oxide (c-IGZO) on glass substrate was deposited and characterized. The crystallinity of IGZO in the active layers is all highly crystallized by nano-beam electron diffraction (NBED) analysis. High-resolution transmission electron microscopy (HRTEM) image shows the formation of c-IGZO with c-axis alignment. The main peak of the c-IGZO is in (009) planes by X-ray diffraction (XRD). The d-spacing in NBED pattern by comparing with the d-spacing of Silicon wafer in NBED pattern is 2.9 Å, which almost equals to the value of powder diffraction file (PDF) data base of InGaZnO4.[1]

42‐3L: Late‐News Paper: Development of Crystalline IGZO and LTPS Hybrid TFTs Array Technology

“…The electrical characteristics of c-IGZO TFTs and n-channel LTPS TFTs were measured by HP-4156B semiconductor parameter analyzer. Figure 1(a) shows the HRTEM image of cross-section of c-IGZO film, which exhibits highly preferring orientation and alignment perpendicular to the surface of a film [1]. The characteristic peak of the c-IGZO film was observed by out-of-plan X-ray diffraction (XRD) in Figure 1(b).…”

“…The c-IGZO thin film on 320mmx400mm glass substrate with our crystallized techniques has been developed. It shows good quality of crystal grain size and clear crystallization properties of IGZO from high-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) patterns [1]. In this study, we furthermore apply self-developed c-IGZO techniques to larger substrate and show its crystallization characteristics by XRD, HRTEM, and nano-beam electron diffraction (NBED) and the crystallization uniformity using selected area electron diffraction (SAED).…”

12‐4: Late-News Paper: Reliability Improvement of IGZO and LTPS Hybrid TFTs Array Technology

“…That is, the active layers of IGZO and LTPS are on the same plane of buffer layer top surface. The remaining processes are similar to LTPS TFT process after poly silicon layer (2)…”