Overview of logical bases and microcircuits in the construction of a combination device taking into account reliability

Abstract

The fundamental laws of the positive algebra of logic are considered, including the rules relating to the elements of equivalence and non-equivalence. Logic gates used in practice are presented. The whole set of standard schemes is implemented, in particular, the frontal version, minimized, in the "OR–NOT" basis, in the "AND–NOT" basis based on the initial logical dependence: ¬(¬(A¬B) × ¬(¬CD) + ¬(¬AB) × ¬(C¬D)) + ¬(¬(AB) × ¬(CD) + ¬(¬A¬B) × ¬(¬C¬D)) . A combination device based on K176LE5 chips has been designed. It is noted that the implementation of this function requires at least 3 chips in the Pier basis, which is not optimal in terms of reliability and weight and size indicators. The transition from the minimized variant to the basis of "Non-Equivalence" + "Conjunction", as well as the basis of "Equivalence" + "Pierce function" is carried out. The results of the search for existing chips that implement the functions "Exclusive OR", "AND", "Exclusive OR–NOT" and "OR-NOT" are presented. 4 groups of chips were found, such as: chips based on logic with emitter coupling (ECL), based on transistor-transistor logic (TTL), based on a series of CMOS chips: with a supply voltage of 5-15 V, and also with a supply voltage of 3-5 V. The corresponding descriptions of each of the MC10H1xx chips (group 1 series); K155xx, xx74xx (group 2 series); K561xx, CD40xxxx (group 3 series); SN74LVCxxx (group 4 series) are presented. Implementation options for these groups of chips in both bases are presented. The cost analysis of the applied microcircuits is made. The calculation of the final cost of products is presented. The conclusion is made about the expediency of using one or another group of microcircuits, depending on the initial requirements set.

Improving the quality indicators and performance of logical blocks and static memory of the microprocessor as part of improving the energy efficiency of devices

“…Logic circuits are characterized by single transient type failures (DSET), which increase in importance as the operating frequency increases and the clock period decreases. Especially dangerous are failures in the clock circuits, which can lead to serious disruptions in the operation of the device [11,14,15] In VLSIs with increased durability (such as microprocessors or systems-on-a-chip), the clock circuits are protected first [12,[16][17][18].…”

“…A common option for protecting memory circuits is the DICE cell [10][11][12][13] (Dual Interlocked Cell), shown in Fig. 6.…”

Quality indicators in methodology for designing RAM units as part of microprocessor systems in digital devices used in environmental engineering

“…When a heavy charged particle enters the body of the transistor, electron-hole pairs are formed, which can be separated in the strong electric field of the drain p-n junction. As a result, the main charge carriers can accumulate in the body of the transistor, which leads to an increase in the potential of the body, opening of the source p-n junction and the inclusion of a parasitic bipolar structure [6][7][8]. Thus, in contrast to a bulk MOSFET, in SOI the main volume sensitive to TPC is the drain p-n junction only on the side of the transistor body; the bottom part of the drain p-n junction is blocked by a hidden oxide.…”