Overlay improvement by ASML HOWA 5th alignment strategy

Wang, Raf; Cy, Chiang; Hsu, Wilson; Yang, Richer; Shih, Todd; Chen, Jackie; Chiu, Jonathan; Lin, Wythe

doi:10.1117/12.839816

Cited by 6 publications

(6 citation statements)

References 2 publications

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“…As an important subsystem of the scanner, the alignment system significantly influences the overlay error; therefore, high-precision alignment is a necessary but inadequate condition for high-precision overlay control. In terms of the data processing of overlay error, the alignment position deviation (APD) is measured before exposing, being followed by the correction of the positions and adjustment of the stage system to reduce the alignment error 22 . While the overlay measurement is operated after exposing, and the analyzed overlay data are used to examine whether the overlay accuracy is acceptable and are transmitted to support the PC step.…”

Section: Overlaymentioning

confidence: 99%

Review of overlay error and controlling methods in alignment system for advanced lithography

Hao¹,

Qi²

2022

Thirteenth International Conference on Information Optics and Photonics (CIOP 2022)

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Acting as one of the three critical indicators to evaluate the performance of lithography scanners, overlay has been a vital factor which seriously affects the electric property, life span and reliability of integrated circuits (IC). With continuous developments of technology nodes and applications of resolution enhancement technologies (RET), current resolution of the scanners has shrunk to 7 nm and beyond, proposing more stringent requirements for measuring, monitoring and correcting the overlay error. To ensure that the overlay budget fully met by the scanner, advanced optical technologies and holistic alignment approaches have been gradually applied to the alignment system of the scanner, revealing that an integrated methodology in which multiple technologies are adopted proved to be valid and effective in reducing the overlay error in present technology nodes.In this article, the exact concept of overlay error is provided, and on this basis different methods to describe the overlay error are comprehensively analyzed from the perspectives of classifications, sources, quality control and correcting models. Then the systematic relationship between alignment and overlay is illustrated. Recent improvements in the alignment system are also the key points here to systematically reduce the overlay error, including the optimization of the alignment optical path, mark types and design procedures, as well as the application of optimal color weighting (OCW), wafer alignment model mapping (WAMM) and sampling scheme optimization (SSO) algorithms. Based on the combined application and iteration of these technologies, it is believed that the on-product overlay (OPO) can be further compressed to support the continuous tightening of the overlay budget in the industry of IC.

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Section: Overlaymentioning

confidence: 99%

Review of overlay error and controlling methods in alignment system for advanced lithography

Hao¹,

Qi²

2022

Thirteenth International Conference on Information Optics and Photonics (CIOP 2022)

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“…However, such requirements are difficult to achieve because overlay accuracy is not proportional to the lithography resolution in double patterning or NGL. It is shown that overlay errors include wafer alignment errors, process effects induced errors, metrology and feedback model errors and so on [5]. Only wafer alignment error during lithography process is considered in this article.…”

Section: Introductionmentioning

confidence: 99%

New alignment mark designs in single patterning and self-aligned double patterning

Zhang

Dong

et al. 2017

Microelectronic Engineering

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“…Wafer alignment in the scanner correlates with overlay performance, and therefore any improvement to the alignment marks 20 , sampling procedure, and modeling, can lead to better overlay. By applying high-order wafer alignment together with an optimized sampling has been reported to reduce uncorrectable overlay residual by 30-40% and significantly improve wafer-to-wafer overlay variation 21 . Overlay improvement by means of scanner control includes applying high-order grid corrections, intra-field high-order process correction (iHOPC), and correction per exposure (CPE) 22 .…”

Section: Introductionmentioning

confidence: 99%

Evaluation of double-patterning techniques for advanced logic nodes

et al. 2010

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The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

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Overlay improvement by ASML HOWA 5th alignment strategy

Cited by 6 publications

References 2 publications

Review of overlay error and controlling methods in alignment system for advanced lithography

Review of overlay error and controlling methods in alignment system for advanced lithography

New alignment mark designs in single patterning and self-aligned double patterning

Evaluation of double-patterning techniques for advanced logic nodes

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