Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs

Miki, Takuji; Nagata, Makoto; Tsukioka, Akihiro; Miura, Noriyuki; Okidono, Takaaki; Araga, Yuuki; Watanabe, Naoya; Shimamoto, H.; Kikuchi, Katsuya

doi:10.1109/3dic48104.2019.9058860

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Ic Chip Packaging and Assembly1

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Cited by 2 publications

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“…The shielding layers on an IC chip use metal wiring channels densely in parallel with encrypted signaling on the topmost metal layer [56]. An additional chip having low-impedance PDN structures is placed on top of a secure IC die in the 3-D integration [57]. The shielding materials conformally formed in IC chip packaging are conductive to attenuate or magnetic to absorb EM radiations from the circuits [58]- [60].…”

Section: Ic Chip Packaging and Assemblymentioning

confidence: 99%