Output Impedance Mismatch Effects on the Linearity Performance of Digitally Predistorted Power Amplifiers

A new, dynamic, double-input, double-output (DIDO), wideband, dynamic, complex envelope, behavioral model for power amplifiers (PAs), accounting for load mismatch effects, is proposed and validated in this paper. The model is constructed based on two-dimensional, dynamic, canonical section-wise piecewise-linear functions (2-D DCSWPL). Compared with existing DIDO behavioral modeling methods, which are almost all exclusively based on polynomial functions, the proposed model permits a vastly extended modeling space for PAs under load mismatch conditions. Experimental examples are given to validate the proposed modeling technique with a 15 W GaN PA under a wide range of output mismatch conditions, driven by a 5 MHz LTE signal. The proposed model shows an average accuracy improvement of 2 dB when compared with the more traditional DIDO memory polynomial (MP) models. In addition, the load reflection-dependent dynamic 2-D CSWPL modeling technique for PAs under mismatch condition is also provided. Compared with load-dependent MP, load-dependent crossover MP (COMP) and load-dependent DIDO MP models, the proposed model shows superior accuracy. Thus, the proposed modeling technique is an excellent choice for the modelling of PA systems that are subject to load mismatch effects. INDEX TERMS Canonical section-wise piecewise-linear Function, dynamic modeling, load mismatch effects, nonlinear behavioral Modeling, RF PAs.

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“…Based on this fact, we can normalize the phase ofx (n), we start from the single input single output case in (11), so that (11) becomes…”

Section: ) Cpl Technique For Conventional Siso Modelmentioning

confidence: 99%

Behavioral Model of RF PAs Including Load Mismatch Effects Based on Canonical Section-wise Piecewise-Linear Function

Cai

King

2020

IEEE Access

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“…For class-E PAs, this degrades the output power, efficiency, linearity and also jeopardizes the reliability [5]. For a polar class-E PA, this translates to variation in AM/AM and AM/PM characteristics, which renders 50 Ω optimized static DPD ineffective under load variation [6].…”

Section: Introductionmentioning

confidence: 99%

Preserving Polar Modulated Class-E Power Amplifier Linearity under Load Mismatch

Khodkumbhe

Huiskamp

Ghahremani

et al. 2020

2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Power amplifiers (PAs) need digital predistortion (DPD) linearization to handle high-order complex modulation schemes in next-generation communication systems. While load variation is inevitable, DPD is generally designed considering only the nominal load impedance for PAs. This paper presents a polar class-E PA with an on-chip waveform characterizer enabling adaptive digital predistortion (ADPD) to preserve the linearity of the PA under load mismatch. The presented ADPD corrects both AM/AM and AM/PM distortions, which are prominent in the demonstrated PA, while simultaneously correcting for slow memory effects without the need for complex memory DPD algorithms. Load-pull measurements demonstrate that target error vector magnitude (EVM) and adjacent channel power ratio (ACPR) can be maintained in a significantly larger area on the Smith chart going from 50 Ω optimized static DPD to our ADPD for a 2 GHz 1024 QAM signal with 1 MSym/s symbol rate.

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“…Recently, the linear power amplifier has become increasingly important to support high speed wireless communication . Accordingly, methods related to improving the linearity of the power amplifier have been vigorously studied.…”

Section: Introductionmentioning

confidence: 99%

A linear CMOS power amplifier using class‐D to reduce the number of required inductors

Son

Yoo

Park

2016

Micro & Optical Tech Letters

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We propose a linear class‐D amplifier for the driver stages of RF CMOS linear power amplifiers. To minimize the chip areas for the driver stages of the linear power amplifiers, we propose a technique for the class‐D amplifier to be operated as a linear amplifier. The linear gain and proper bias point for the linear operation are obtained with additional load capacitance and a feedback resistor, respectively. To verify the feasibility of the proposed linear class‐D amplifier, we designed a 1.8‐GHz CMOS linear power amplifier with a differential structure using 180‐nm RF CMOS technology. From the measured linearity and maximum average output power with a WCDMA modulated input signal, we successfully verify the linear operation of the proposed linear class‐D amplifier. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:565–569, 2016

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Output Impedance Mismatch Effects on the Linearity Performance of Digitally Predistorted Power Amplifiers

Cited by 29 publications

References 39 publications

Behavioral Model of RF PAs Including Load Mismatch Effects Based on Canonical Section-wise Piecewise-Linear Function

Behavioral Model of RF PAs Including Load Mismatch Effects Based on Canonical Section-wise Piecewise-Linear Function

Preserving Polar Modulated Class-E Power Amplifier Linearity under Load Mismatch

A linear CMOS power amplifier using class‐D to reduce the number of required inductors

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