Highly efficient switch-mode Class-E power amplifiers (PAs) are sensitive to load impedance variations. For voltage standing wave ratios (VSWRs) up to 10:1, the peak switch voltage and average switch current can increase by a factor 1.7 and 2.5, respectively, with respect to the nominal load condition, thereby imposing serious reliability risks. This work introduces a technique to self-protect/self-heal Class-E PAs against the effects of load variations, with only a minor impact on output power and efficiency. To validate the proposed technique, load-pull measurements are conducted on a Class-E PA implemented in a standard 65nm CMOS technology, employing an off-chip matching network, augmented with a fully automated self-protective/self-healing control loop. Under nominal operating conditions, the PA provides 17.5dBm output power into 50Ω from a 1.2V supply with 67% efficiency when all the losses of the matching network are included. It is shown that the proposed self-protective PA can reduce its peak switch voltage to below the value allowed by the technology for all load mismatch conditions with VSWR up to 19:1 while output power and efficiency are not considerably affected. Furthermore, a PA with an average current safety factor of 2.5 can reliably handle VSWRs up to 19:1.
A two channel 65 nm CMOS RF-waveform characterizer is presented that enables multi-harmonic Adaptive Matching Networks (AMN) or Adaptive Digital Pre-Distortion (ADPD) in RF-power amplifiers. The characterizer measures the DC component and the first 3 harmonics of RF signals by applying a DFT to 8 (ideally) equally spaced quasi-DC output voltages. Conventionally in these types of systems accuracy is limited by sample timing accuracies, which in our case are mainly due to delay cell mismatch. We introduce a novel way to cancel delay cell mismatch, that significantly increases measurement accuracy at the cost of only a small power and area increase. The RF-waveform characterizer achieves 6.8-bit measurement linearity together with a (clock feedthrough limited) 24 dB SFDR. The measured power consumption for our proof-of-principle demonstrator is 18.6 mW at a maximum input signal frequency of 1.1 GHz under continuous operation.
Highly efficient switch-mode class-E Power Amplifiers (PAs) are sensitive to load impedance variations. For Voltage Standing Wave Ratios (VSWRs) up to 10:1, the peak switch voltage and average switch current can increase by a factor 1.7 and 2.5, respectively, relative to those under nominal load conditions, imposing serious reliability risks. This work describes a technique to self-protect class-E PAs to decrease their sensitivity to load variations, relying on tuning of the switch-tank relative-resonance frequency, implemented by an on-chip Switched-Capacitor Bank (SCB). To validate the technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65 nm CMOS technology, employing an off-chip matching network, augmented with a fully automated self-protective control loop. Under nominal conditions, the PA provides 17.8 dBm at 1.4 GHz into 50 Ω from a 1.2 V supply with 67% efficiency. The proposed self-protective PA can reduce its peak switch voltage below the technology-and switch design-related limit for any load with a VSWR up to 19:1, while not considerably impacting output power and efficiency, which see a maximum degradation of 1.6 dB and 6%, respectively. Furthermore, a class-E PA designed to safely handle 2.5× the nominal average switch current can reliably operate for VSWRs up to 19:1 when protected with our technique.
Power amplifiers (PAs) need digital predistortion (DPD) linearization to handle high-order complex modulation schemes in next-generation communication systems. While load variation is inevitable, DPD is generally designed considering only the nominal load impedance for PAs. This paper presents a polar class-E PA with an on-chip waveform characterizer enabling adaptive digital predistortion (ADPD) to preserve the linearity of the PA under load mismatch. The presented ADPD corrects both AM/AM and AM/PM distortions, which are prominent in the demonstrated PA, while simultaneously correcting for slow memory effects without the need for complex memory DPD algorithms. Load-pull measurements demonstrate that target error vector magnitude (EVM) and adjacent channel power ratio (ACPR) can be maintained in a significantly larger area on the Smith chart going from 50 Ω optimized static DPD to our ADPD for a 2 GHz 1024 QAM signal with 1 MSym/s symbol rate.
INTEGRATED MEASUREMENT TECHNIQUES FOR RF-POWER AMPLIFIERS PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. ir. A. Veldkamp, volgens besluit van het College voor Promoties in het openbaar te verdedigen op woensdag 2 februari 2022 om 14:45 uur door Maikel Huiskamp geboren op
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