Oscillation ring based interconnect test scheme for SOC

Li, Katherine Shu-Min; Lee, Chung Len; Su, Chauchin; Chen, Jwu E.

doi:10.1145/1120725.1120800

Cited by 25 publications

(15 citation statements)

References 6 publications

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“…Oscillation ring (OR) test is a useful and efficient method to detect faults in SOC interconnect [9]. An oscillation ring is a closed loop of a circuit under test in which has an odd number of signal inversions.…”

Section: The or Test Architecture For Interconnectmentioning

confidence: 99%

“…In additional to the normal input/output connections, all wrapper cells in a core can also be connected with a shift register, which is usually referred to as a scan path, to facilitate test access. A modified wrapper cell design has been proposed to provide extra connections and inversion control so that the oscillation rings can be constructed through the wires and the boundary scan paths in cores [9]. For example, the ring in Figure 2 consists of one oscillation ring and a neighboring net, and two scan paths in cores C 1 and C 2 form the oscillation ring.…”

Section: The or Test Architecture For Interconnectmentioning

confidence: 99%

“…The circuit structure of an SOC can be directly transformed into a hypergraph, in which each vertex denotes a pin while each hypernet represents a signal net. However, this graph model is not good enough for the OR test problem, as two branches of a net should belong to two different rings, and they cannot be tested simultaneously [9]. Therefore, it would be better to consider each branch of a hypernet separately, instead of treating them as a whole.…”

Section: Interconnect Model In Oscillation Ring Testmentioning

confidence: 99%

“…The TAM defines the test control, while the wrappers provide a standardized interface for test data transmission. An oscillation ring test (ORT) [9] method for interconnect test was proposed to detect not only stuck-at and open faults, but also delay and crosstalk glitch faults. Many testing and diagnosis problems are incurred by particular interconnect structures, which can be partly solved by carefully determining the interconnect structures.…”

Section: Introductionmentioning

confidence: 99%

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Multilevel full-chip routing with testability and yield enhancement

Lee

Chang

et al. 2005

Proceedings of the 2005 International Workshop on System Level Interconnect Prediction

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We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the popular IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening followed by uncoarsening by introducing a preprocessing stage that analyzes the oscillation ring structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [24], the experimental results show that our router improves the maximal congestion by 1.24X--6.11X in runtime speedup by 1.08X--7.66X, and improves the average congestion by 1.00X--4.52X with the improved congestion deviation by 1.37X--5.55X.

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Section: The or Test Architecture For Interconnectmentioning

confidence: 99%

Section: The or Test Architecture For Interconnectmentioning

confidence: 99%

Section: Interconnect Model In Oscillation Ring Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Multilevel full-chip routing with testability and yield enhancement

Lee

Chang

et al. 2005

Proceedings of the 2005 International Workshop on System Level Interconnect Prediction

Self Cite

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“…To the best of our knowledge, prior work (e.g., [2,5,14,24]) has not taken these issues into consideration. The approach employed in prior work is to simply let all involved core wrapper cells transit concurrently with the same test clock signal [6].…”

Section: Introductionmentioning

confidence: 99%

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs

Zhang

Chakrabarty

2007

2007 IEEE International Test Conference

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IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

Li¹,

Chang

et al.

Asia and South Pacific Conference on Design Automation, 2006.

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Abstract-An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution.

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Oscillation ring based interconnect test scheme for SOC

Cited by 25 publications

References 6 publications

Multilevel full-chip routing with testability and yield enhancement

Multilevel full-chip routing with testability and yield enhancement

Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs

IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

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