Visualization of circuits is an important research area in electronic design and automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses orthogonal lines to connect the gates. Our approach introduces the restriction that every net is allowed to occupy only one track. This avoids unnecessary bends in the wires and helps to improve the clarity of the drawing. Then a crossing reduction step is applied to further improve the readability of the circuit schematics.In this paper we assume that the nodes have already been fixed on a layered hypergraph structure. We consider the problem of assigning the hyperedges between two layers to tracks. The idea is to minimize the total number of hyperedge crossings. First, we prove that finding the best solution is NP-hard. Then, we present a new heuristic to reduce the number of crossings. Finally, some promising experimental results on real circuits are given. The results show that in the majority of cases, the layout produced by our algorithm are within 3% of the optimal solution.