Orthogonal Hypergraph Drawing for Improved Visibility

Abstract

Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses orthogonal lines to connect the gates. In our model we assume that between two consecutive layers every net is allowed to occupy only one track. This avoids unnecessary bends in the wires and helps to improve the clarity of the drawing. Then a crossing reduction step is applied to further improve the readability of the circuit schematics.First we assume that the nodes have already been fixed on a layered hypergraph structure. We consider the problem of assigning the hyperedges between two layers to tracks. The idea is to minimize the total number of hyperedge crossings. We prove that finding the best solution is NP-hard. Then, in contrast to many other approaches which route all the wiring after placing all nodes we focus on a new approach which dynamically reorders the nodes within the layers to further reduce the number of hyperedge crossings. An efficient algorithm is presented that minimizes the hyperedge crossings. Experimental results are provided which show that the drawings can be improved significantly while the running time remains moderate.

Port Constraints in Hierarchical Layout of Data Flow Diagrams

“…Other unpublished solutions to drawing with port constraints include ILOG JViews [18] and Tom Sawyer Visualization 4 . Handling of hyperedges in hierarchical layout has been covered by Eschbach et al [10] and Sander [17]. Sugiyama et al [21] and Sander [16] showed how to draw general compound graphs, but due to the presence of external ports (see Section 2), our requirements for compound graphs are different.…”

“…Although there are approaches to directly handle hyperedges [10,17], we split all hyperedges into sets of plain edges in order to simplify the algorithms. For this reason we consider all edges that are incident at the same port of a vertex as parts of a single hyperedge.…”

“…The resulting routing slots are sorted and given appropriate horizontal positions, and each edge that has p as source port is given two bend points with the respective horizontal position of s(p). We employ the basic sorting of routing slots as depicted by Eschbach et al [10], but have to extend it to support the different scenarios of port positions. An additional difficulty arises when the source port of an edge is not on the right side of the source vertex, or the target port is not on the left side of the target vertex.…”

“…Sugiyama et al [21] and Sander [16] showed how to draw general compound graphs, but due to the presence of external ports (see Section 2), our requirements for compound graphs are different. We adapt the orthogonal edge routing approach suggested by Eschbach et al [10]; alternative approaches have been given by Sander [15,17] and Baburin [2].…”

Subdivision Drawings of Hypergraphs

“…In relational databases there is a natural correspondence between database schemata and hypergraphs, with attributes corresponding to vertices and relations to hyperedges [7]. Hypergraphs are used in VLSI design for circuit visualization [6,14] and also appear in computational biology [10,12] and social networks [3].…”