Origin of Subthreshold Swing Improvement in Amorphous Indium Gallium Zinc Oxide Transistors

Jeong, Jae Hoon; Yang, Hai; Park, Jin‐Seong; Jeong, Jae Kyeong; Mo, Yeon‐Gon; Kim, Hye Dong; Song, Jaewon; Hwang, Cheol Seong

doi:10.1149/1.2903209

Cited by 222 publications

(134 citation statements)

References 11 publications

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“…In addition, it has been reported that the trap density of the channel layer is correlated with its density. 46 X-ray reflectivity (XRR) was used to analyze the quality of the bulk of the films AIP Advances 5, 017116 (2015) ( Fig. 2(b)).…”

Section: /Cmmentioning

confidence: 99%

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

et al. 2015

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The stable operation of transistors under a positive bias stress (PBS) is achieved using Hf incorporated into InOx-based thin films processed at relatively low temperatures (150 to 250 °C). The mobilities of the Hf-InOx thin-film transistors (TFTs) are higher than 8 cm2/Vs. The TFTs not only have negligible degradation in the mobility and a small shift in the threshold voltage under PBS for 60 h, but they are also thermally stable at 85 °C in air, without the need for a passivation layer. The Hf-InOx TFT can be stable even annealed at 150 °C for positive bias temperature stability (PBTS). A higher stability is achieved by annealing the TFTs at 250 °C, originating from a reduction in the trap density at the Hf-InOx/gate insulator interface. The knowledge obtained here will aid in the realization of stable TFTs processed at low temperatures.

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Section: /Cmmentioning

confidence: 99%

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

et al. 2015

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“…In particular, its electrical resistivity is wideranging (10 10 -10 -4 Ω) because the ns-orbital of the metal cation is larger than the 2p-orbital of oxygen anion [11]. Thus, many studies have mainly focused on controlling the performance of the a-IGZO device, which is dependent on various susceptible parameters such as sputtering power and post-treatment [12][13][14]. The thickness of the channel layer can also be an important parameter to control device performance.…”

Section: Introductionmentioning

confidence: 99%

Effect of oxygen on the threshold voltage of a-IGZO TFT

Chong¹,

Chun²,

Kim³

et al. 2011

Journal of Electrical Engineering and Technology

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-Thin-film transistors (TFTs) are fabricated using an amorphous indium gallium zinc oxide (a-IGZO) channel layer by rf-magnetron sputtering. Oxygen partial pressure significantly changed the transfer characteristics of a-IGZO TFTs. Measurements performed on а-IGZO TFT show the change of threshold voltage in the transistor channel layer and electrical properties with varying O 2 ratios. The device performance is significantly affected by adjusting the O 2 ratio. This ratio is closely related with the modulation generation by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.

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“…It has been reported that the densification of IGZO film reduced bulk defects above Fermi-level in the TFT channel. 33 However, our result also indicates that the densification of the IGZO film reduces bulk defects below Fermi-level in the TFT channel as well.…”

Section: Resultsmentioning

confidence: 56%

Quantitative Analysis of Hole-Trapping and Defect-Creation in InGaZnO Thin-Film Transistor under Negative-Bias and Illumination-Stress

Hung

Wang

Toda

et al. 2014

ECS J. Solid State Sci. Technol.

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We report two measurement methods, named positive gate pulse mode (PGPM) and double sweeping mode (DSM), which can estimate the hysteresis induced by hole trapping in a gate insulator ( V hole ) and by defect creation in the IGZO channel ( V defect ). The effects of IGZO deposition temperature and of stress temperature on defect creation in the channel under negative bias and illumination stress (NBIS) are investigated. The results show that high deposition temperature of IGZO reduces defect creation in the channel under NBIS. The average activation energy for hole trapping in a GI under NBIS has been calculated to be 0.39 eV. InGaZnO (IGZO) thin-film transistors (TFTs) with field effect mobility >10 cm 2 /(V · s) are now used in high definition, large area ether active matrix liquid crystal displays (AMLCD) and active matrix organic light emitting diode displays (AMOLED).1,2 However, the reliability of IGZO TFTs under negative bias and illumination stress (NBIS) still requires improvement. Three possible reasons for NBIS instability in IGZO TFTs have been reported: (i) hole trapping in a gate insulator (GI), 3,4 (ii) donor like defect creation in the IGZO channel, [5][6][7] and (iii) electron trapping at a back channel interface. 8 Many efforts to improve NBIS reliability of IGZO TFT have been reported. 9-14 Hole trapping at front channel interface could be reduced by using AlO x as a gate insulator 9 or by using TiO 2 as a hole blocking layer. 14 The donor like state creation could be reduced by annealing IGZO TFTs in a high pressure water vapor, 10 wet O 2 , 11 hydrogen environment. 12 An AlO x , SrO x passivation layer could be used to suppress deep subgap defects in the IGZO channel. 13 In our previous study, 8 both hole trapping in a GI and donor like state creation in an IGZO channel induced hysteresis (V h ) in an IGZO TFT under NBIS. However, unlike a-Si TFT, the NBIS degradation mechanism in IGZO TFT is not consistent. It depends on the TFT structure, 15 the IGZO composition 16 and the fabrication process.17 Therefore, an understanding of the contribution of hole trapping in a GI and donor like state creation in an IGZO channel to V h is essential in the work to improve oxide TFT stability.Capacitance-voltage measurement is usually used to detect defect creation in the IGZO channel. 18,19 Subthreshold voltage swing [Ss = dV g /d log I D (V/decade)] could also be used to estimate the total number of generated defects ( N defect ) using the equation:[1]The threshold voltage shift induced by generated defects ( V defect ) can be calculated using the following equation:where C i is gate capacitance per unit area, q is the elementary charge, K is the Boltzmann constant and T is the absolute temperature (K). However, to the best of our knowledge, there is no direct method for separately measuring of hysteresis induced by trapped hole in a gate insulator ( V hole ) and hysteresis induced by defect creation in a channel ( V defect ). In this study, we demonstrate our developed measurement method, referred to i...

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Origin of Subthreshold Swing Improvement in Amorphous Indium Gallium Zinc Oxide Transistors

Cited by 222 publications

References 11 publications

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Effect of oxygen on the threshold voltage of a-IGZO TFT

Quantitative Analysis of Hole-Trapping and Defect-Creation in InGaZnO Thin-Film Transistor under Negative-Bias and Illumination-Stress

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