Quantitative Analysis of Hole-Trapping and Defect-Creation in InGaZnO Thin-Film Transistor under Negative-Bias and Illumination-Stress

Abstract

We report two measurement methods, named positive gate pulse mode (PGPM) and double sweeping mode (DSM), which can estimate the hysteresis induced by hole trapping in a gate insulator ( V hole ) and by defect creation in the IGZO channel ( V defect ). The effects of IGZO deposition temperature and of stress temperature on defect creation in the channel under negative bias and illumination stress (NBIS) are investigated. The results show that high deposition temperature of IGZO reduces defect creation in the channel under NBIS. The average activation energy for hole trapping in a GI under NBIS has been calculated to be 0.39 eV. InGaZnO (IGZO) thin-film transistors (TFTs) with field effect mobility >10 cm 2 /(V · s) are now used in high definition, large area ether active matrix liquid crystal displays (AMLCD) and active matrix organic light emitting diode displays (AMOLED).1,2 However, the reliability of IGZO TFTs under negative bias and illumination stress (NBIS) still requires improvement. Three possible reasons for NBIS instability in IGZO TFTs have been reported: (i) hole trapping in a gate insulator (GI), 3,4 (ii) donor like defect creation in the IGZO channel, [5][6][7] and (iii) electron trapping at a back channel interface. 8 Many efforts to improve NBIS reliability of IGZO TFT have been reported. 9-14 Hole trapping at front channel interface could be reduced by using AlO x as a gate insulator 9 or by using TiO 2 as a hole blocking layer. 14 The donor like state creation could be reduced by annealing IGZO TFTs in a high pressure water vapor, 10 wet O 2 , 11 hydrogen environment. 12 An AlO x , SrO x passivation layer could be used to suppress deep subgap defects in the IGZO channel. 13 In our previous study, 8 both hole trapping in a GI and donor like state creation in an IGZO channel induced hysteresis (V h ) in an IGZO TFT under NBIS. However, unlike a-Si TFT, the NBIS degradation mechanism in IGZO TFT is not consistent. It depends on the TFT structure, 15 the IGZO composition 16 and the fabrication process.17 Therefore, an understanding of the contribution of hole trapping in a GI and donor like state creation in an IGZO channel to V h is essential in the work to improve oxide TFT stability.Capacitance-voltage measurement is usually used to detect defect creation in the IGZO channel. 18,19 Subthreshold voltage swing [Ss = dV g /d log I D (V/decade)] could also be used to estimate the total number of generated defects ( N defect ) using the equation:[1]The threshold voltage shift induced by generated defects ( V defect ) can be calculated using the following equation:where C i is gate capacitance per unit area, q is the elementary charge, K is the Boltzmann constant and T is the absolute temperature (K). However, to the best of our knowledge, there is no direct method for separately measuring of hysteresis induced by trapped hole in a gate insulator ( V hole ) and hysteresis induced by defect creation in a channel ( V defect ). In this study, we demonstrate our developed measurement method, referred to i...

Effects of Hydroxyl Group in AlOx Gate Insulator on the Negative Bias Illumination Instability of In‐Ga‐Zn‐O Thin Film Transistors

“…The direct injection and/or trapping of photo‐generated holes and/or ionized oxygen vacancies (, ), into the gate dielectric bulk have been suggested to be the main mechanisms of NBIS . Intensive studies related to the NBIS instability mechanism have revealed that not only holes but also oxygen vacancies ( V o ) are related to the NBIS instability . Recently, Jia et al, reported that cation vacancy also a possible reason for NBIS instability .…”

Densification of a-IGZO with low-temperature annealing for flexible electronics applications

“…Additionally, there are numerous works in which increases in density have been correlated to improvements in device performance, supporting this theoretical work, achieved through variations in deposition parameters. [34][35][36] It is therefore possible to monitor the reduction of these defects by measurement of the material density as a function of annealing. While the effect of higher temperature annealing, >250 C, on the electronic properties and on material structure, has been well explored, 27,28,37 the impact of low-and intermediate-temperature annealing (<300 C), compatible with fabrication of TFTs on flexible substrates, has received little attention, particularly in relation to the temporal aspect.…”

P‐18: Extraction and Simulation with Time Dependent Vth Shift Model for IGZO Panel

“…The difference between them is the V th increase due to charge trapping when the TEG is turned on. The amount of the V th increase is calculated by summing the V th increase at each V GS bias and can be expressed as the extended-exponential equations [5]…”

“…In addition to the constant gate and/or drain biases stresses, the remarkable impact of visible-light on the characteristics of IGZO TFT has been reported. The reliability of IGZO TFTs under the negative bias and illumination stress (NBIS) which is caused by the hole trapping in a GI and/or a GI/IGZO interface, the creation of ionized oxygen vacancies (V o + or V o2 + ) [4], the donor-like defects in IGZO TFT channel, and electron trapping at a back channel interface [5][6] and the illuminated positive gate-bias stress which performs a superior stability than the dark stress [7] have been reported. Besides DC static stress studies of the IGZO TFT, the AC and dynamic stress behavior and mechanisms have been investigated recently [8] [9] because the estimating degradation behavior may not be correct for practical circuit designs when considering DC static bias stresses only.…”