2015
DOI: 10.1063/1.4905903
|View full text |Cite
|
Sign up to set email alerts
|

Reduction of the interfacial trap density of indium-oxide thin film transistors by incorporation of hafnium and annealing process

Abstract: The stable operation of transistors under a positive bias stress (PBS) is achieved using Hf incorporated into InOx-based thin films processed at relatively low temperatures (150 to 250 °C). The mobilities of the Hf-InOx thin-film transistors (TFTs) are higher than 8 cm2/Vs. The TFTs not only have negligible degradation in the mobility and a small shift in the threshold voltage under PBS for 60 h, but they are also thermally stable at 85 °C in air, without the need for a passivation layer. The Hf-InOx TFT can b… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

1
6
0

Year Published

2015
2015
2022
2022

Publication Types

Select...
7

Relationship

1
6

Authors

Journals

citations
Cited by 17 publications
(7 citation statements)
references
References 53 publications
1
6
0
Order By: Relevance
“…Hence, the favorable change in V TH is partly attributed to the influence of T in deep trap formation, which means that fewer deep hole traps exist in the channel when CuSeCN layers are annealed at 140–160 °C. This hypothesis is consistent with previous reports on deep trap formation in inorganic semiconductors such as metal oxides, and its impact on TFT performance . Interestingly, Table S2 (Supporting Information) shows that the subthreshold swing (SS) of TG‐BC transistors is substantially improved when CuSeCN layers are annealed at higher temperatures (140–160 °C).…”
Section: Application Of Cusecn In Opto/electronic Devicessupporting
confidence: 91%
“…Hence, the favorable change in V TH is partly attributed to the influence of T in deep trap formation, which means that fewer deep hole traps exist in the channel when CuSeCN layers are annealed at 140–160 °C. This hypothesis is consistent with previous reports on deep trap formation in inorganic semiconductors such as metal oxides, and its impact on TFT performance . Interestingly, Table S2 (Supporting Information) shows that the subthreshold swing (SS) of TG‐BC transistors is substantially improved when CuSeCN layers are annealed at higher temperatures (140–160 °C).…”
Section: Application Of Cusecn In Opto/electronic Devicessupporting
confidence: 91%
“…For In 2 O 3 , oxygen deficiency formation is inevitable owing to its low formation energy, 13 and therefore oxygen binders such as Hf, W, and Si must be doped to achieve a low trap density which leads to high quality In 2 O 3 -based films. 14,15 The addition of dopants requires higher annealing temperatures to achieve a satisfactory level of field effect mobility as that of undoped In 2 O 3 . It is therefore advantageous to produce In 2 O 3 TFTs without using dopants to maintain low annealing temperatures.…”
Section: Introductionmentioning
confidence: 99%
“…3 The major drawbacks however of polycrystalline In2O3 are related to the grain boundaries formation that cause electrical inhomogeneities and poor control of background carrier concentration that results in high off-currents. To suppress crystallization, several reports on TFTs implementing semiconducting channels based on In2O3 have focused on InGaZnO, 4,5,6,7,8 InZrZnO, 9,10 InHfZnO, 11,12,13,14 InWZnO, 15 InSiZnO, 16,17 InScZnO, 18 InTaZnO, 19 InBZnO, 20 InCZnO, 21 InGaO, 22 InGeO, 23 InHfO, 24 InSiO, 25 , 26 InWO, 27 and InZnO, 28,29 however works on doped In2O3 have also been reported. 25,30,31,32,33,34 In most cases, those In2O3-based semiconductors have been processed by a large number of vacuum-based and potentially costly techniques such as Atomic Layer Deposition, Sputtering, Pulsed Laser deposition, and e-beam deposition.…”
mentioning
confidence: 99%