Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

Lin, Horng−Chih; Hung, Cheng Hsiung; Chen, Wei Chen; Lin, Zer Ming; Hsu, Hsing Hui; Hunag, Tiao Yuang

doi:10.1063/1.3086271

Cited by 38 publications

(25 citation statements)

References 9 publications

(6 reference statements)

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“…To explain clockwise hysteresis at RT that collapses at higher temperatures, we propose a model based on temperature dependent trapping/de-trapping of electrons associated with intrinsic traps in the MoS 2 channel that can only be observed in devices with a fully depleted channel. 38 Schematic energy band diagrams perpendicular to the channel are shown in Fig. 5 for V GS = 100 and −100 V. Onset of RS (100 V) and FS (−100 V) will affect the entire RS and FS range, respectively, considering deep level traps that require times longer than the sweep times to trap/detrap electrons.…”

Section: Resultsmentioning

confidence: 99%

Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

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The origin of threshold voltage instability with gate voltage in MoS 2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS 2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS 2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS 2 on SiO 2 . Additional hysteresis measurements on suspended (~100 nm air gap between MoS 2 and SiO 2 ) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS 2 . At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p + Si gate leads to hysteresis collapse at~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current-voltage (I-V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS 2 transistors have also been demonstrated. npj 2D Materials and Applications (2017) 1:34 ; doi:10.1038/s41699-017-0038-y INTRODUCTION Among two-dimensional materials, graphene 1,2 was the first to be isolated and studied with respect to electronic applications. Due to lack of an energy bandgap in graphene, other 2D materials such as layered transition metal dichalcogenides (TMDs) comprising a wide selection of materials with different bandstructures, and therefore different electrical and optical properties, have garnered significant attention.3-5 Molybdenum disulfide (MoS 2 ) has emerged as a prospective candidate for transistor applications. The presence of a direct bandgap (~1.8 eV) in monolayer form and an indirect bandgap (~1.2 eV) in multilayer MoS 2 makes it a promising channel material for field effect transistors (FETs).

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Section: Resultsmentioning

confidence: 99%

Reversible hysteresis inversion in MoS2 field effect transistors

et al. 2017

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“…The roots of the variances on those performance indices are mainly the charge trapped in gate insulator layer, insulator -LTPS interface, grain-boundary and inside the grains [4] [5]. The density of trap of each type can be derived with different kind of measures including hysteresis, SS and low-high frequency measure [6]- [10]. In addition to the trap concentration, the activation energy of the traps should be noticed too [11].…”

Section: Objective and Backgroundmentioning

confidence: 99%

P‐2: A Novel Method for LTPS Model Extraction with Hysteresis and Transient Current Analysis

Kuo

Tsai

Tseng

et al. 2015

Symp Digest of Tech Papers

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Time-sampling measurements are used in this paper to build time dependent LTPS TFT current model. The device model that considers bias and time dependent threshold voltage (V th ) shift and mobility degradation is implemented in Eldo through GUDM for simulating a pixel circuit as an indicator of panel performance. Author Keywordstime-sampling measurement, LTPS, V th shift, mobility degradation, Eldo, GUDM, transient current. Objective and BackgroundThe performance of a low-temperature poly-silicon (LTPS) thin film transistor (TFT) is usually judged by its threshold voltage (V th ), mobility (), sub-threshold swing (SS) and on-off current ratio (I on /I off ) [1] . In addition to the trap concentration, the activation energy of the traps should be noticed too [11]. Nonetheless, the activation energy of the traps is bias dependent [11]. Therefore, the factors for threshold voltage shift include the gate and drain bias can be expressed as ∆V th = ∆V th (V gs , V ds , Time, Temp). Our goal is to extract the time and bias dependency factor of V th shift from I d -V g and time sampling measure method. The objective of building this model is to enable designers to simulate the image retention time in AMOLED pixel circuit for panel performance estimation. ResultsA P-type LTPS TFT is fabricated with 120nm gate insulator layer and channel dimension of 30μm in length and 3 μm wide. The electrical characteristics were measured in ambient temperature (25℃).When studying the image retention behavior, the chessboard pattern shown in Figure 1 is usually used to observe the image residual phenomenon which is the direct evidence of image retention and the criterion of the panels' quality check. The panel is controlled to display chessboard image for a certain length of time and then switch to pure gray image to observe how long the residual images of previous chessboard image remains. For the pixels, the image change consists of two types of operations, which are white (L255) to gray (L128) and black (L0) to gray (L128). Two panels with different image retention time are selected as the target for examining the effectiveness of the proposed model extraction method. One of them has residual image that lasts 10 seconds, and that of the other lasts 120 seconds. On each panel, one TEG is selected to represent the I-V characteristics of all TFT in the panel. In the following paragraphs, the origins of the residual image will be analyzed and an analytical approach of deriving and extracting the model parameters with transient current will be presented. For an AMOLED panel, the luminance is from the OLED device whose current is controlled by the driving TFT. Therefore, we will focus on the variations of the LTPS TFT because the behavior variations of OLED are within milliseconds and is far from the scale of retention time observed [12]. To mimic the stability of the driving TFT current on a

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“…It is well known that the laser crystallized poly-Si films contain a huge amount of electrical defects at grain boundaries, and these defects degrade their device performance [12], [13]. For example, these electrical defects hinder carrier transport from the source to the drain and significantly decrease carrier mobility, because they act as trapping center for carriers and cause Coulomb scattering.…”

Section: Introductionmentioning

confidence: 99%

Impact of Underwater Laser Annealing on Polycrystalline Silicon Thin-Film Transistor for Inactivation of Electrical Defects at Super Low Temperature

Machida

Horita

Yamaguchi

et al. 2013

J. Display Technol.

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We propose underwater laser annealing (WLA) for the inactivation of electrical defects in polycrystalline silicon thin-film transistors (poly-Si TFTs) at super low-temperature. This technique can reduce the temperature of inactivation process drastically, and it requires only UV laser and deionized water. We performed WLA after the fabrication of top-gate type poly-Si TFTs. After WLA, the field-effect mobility of poly-Si TFTs increased from 52 to 72 cm V sec. The TFT surface was exposed to water vapor which was generated by laser irradiation, resulting that electrical defects were inactivated by active species in water vapor.Index Terms-Thin-film transistor (TFT), polycrystalline silicon (poly-Si), inactivation.

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Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

Cited by 38 publications

References 9 publications

Reversible hysteresis inversion in MoS2 field effect transistors

Reversible hysteresis inversion in MoS2 field effect transistors

P‐2: A Novel Method for LTPS Model Extraction with Hysteresis and Transient Current Analysis

Impact of Underwater Laser Annealing on Polycrystalline Silicon Thin-Film Transistor for Inactivation of Electrical Defects at Super Low Temperature

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