Orientation‐Controlled Selective‐Area Epitaxy of III–V Nanowires on (001) Silicon for Silicon Photonics

Abstract

Monolithic integration of III-V nanowires on silicon platforms has been regarded as a promising building block for many on-chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one of the remaining challenges for on-chip applications is that the growth direction of nanowires on Si(001) substrates is difficult to control. Here, we propose and demonstrate catalystfree selective-area epitaxy of nanowires on ( 001)-oriented silicon-on-insulator (SOI) substrates with the nanowires aligned to desired directions. This is enabled by exposing {111} planes on (001) substrates using wet chemical etching, followed by growing nanowires on the exposed planes. We demonstrate the formation of nanowire array-based bottom-up photonic crystal cavities on SOI(001) and their coupling to silicon waveguides and grating couplers, which support the feasibility for onchip photonic applications. The proposed method of integrating position-and orientationcontrollable nanowires on Si(001) provides a new degree of freedom in combining functional and ultracompact III-V devices with mature silicon platforms.

III–V nanowires on silicon (100) as plasmonic-photonic hybrid meta-absorber

“…Then, silicon nitride is deposited as a dielectric mask and patterned to expose silicon for selective-area epitaxy of III–V nanowires. Next, III–V nanowires are epitaxially grown from the exposed area, where the feasibility of forming such well-ordered nanowire arrays on (111) planes of Si (100) is experimentally demonstrated elsewhere recently 13 . Following the growth of nanowire arrays, BCB polymer is used as a dielectric spacer to adjust the height of exposed nanowires and also to electrically isolate the contacts.…”

“…Although III–V nanowires show great promise for heterointegration with silicon, one of the limitations for practical applications is that III–V nanowires typically grow along <111> direction, not < 100> direction. In other words, vertical nanowires can be grown on <111>-oriented wafers, whereas the growth direction of nanowires on <100>-oriented wafers is angled and random 13 – 15 . Because both the silicon electronics and silicon photonics industry exclusively employ Si (100) or silicon-on-insulator (100) as a standard, the lack of controllability in the growth direction of nanowires on Si (100) substrate undermines the compatibility and degrades the degree of freedom in designing nanowire-based devices on Si (100).…”

“…The proposed design could be fabricated by combining the capability to control the ordering of nanowire arrays on silicon (100) with self-assembled gold plasmonic metasurfaces. Specifically, the orientation of nanowires is aligned to one of the four <111> directions exposed on silicon (100) by employing advanced selective-area epitaxy processes 13 , 16 which allows the integration of III–V materials with low defect density despite the lattice mismatch with silicon, and then gold is deposited to form periodic gold nanoholes which are self-assembled to each nanowire. Finite-difference time-domain (FDTD) simulations reveal that high absorption efficiency in III–V nanowires, which greatly exceeds the fill factor of nanowires, can be achieved by exciting plasmonic-photonic hybrid modes.…”

InAsP Quantum Dot-Embedded InP Nanowires toward Silicon Photonic Applications

“…The results suggest that the proposed method of forming QD-NWs on silicon can be universally applied to obtain ternary QDs in nanowires covering exciton–biexciton emission wavelength in the telecom regime. In this manner, by forming these nanowires on silicon-on-insulator photonic platforms and waveguides which have been recently reported, the QD-NW emitters can be utilized in silicon photonic applications such as wavelength multiplexed nanowire single photon sources. − …”

Monolithic and catalyst-free selective epitaxy of InP nanowires on Silicon

“…In recent years there has been a substantial interest towards monolithically integrating III-V semiconductors with Silicon (Si) due to their extensive applications in electronics 1,2 , optoelectronics [3][4][5] and photonics 6,7 . In particular, indium phosphide (InP) nanowires (NWs) have drawn attention due to their carrier lifetime between 120 ps and 2 ns 8,9 , low surface recombination velocity of about 170 cm s − 110 , and high carrier mobility around 1500 cm 2 V − 1 s − 1 at room temperature 1 , properties that render them outstanding for both light emission and light harvesting applications.…”