Current thermometry techniques lack the spatial resolution required to see the temperature gradients in typical, highly-scaled modern transistors. As a step toward addressing this problem, we have measured the temperature dependence of the volume plasmon energy in silicon nanoparticles from room temperature to 1250$^\circ$C, using a chip-style heating sample holder in a scanning transmission electron microscope (STEM) equipped with electron energy loss spectroscopy (EELS). The plasmon energy changes as expected for an electron gas subject to the thermal expansion of silicon. Reversing this reasoning, we find that measurements of the plasmon energy provide an independent measure of the nanoparticle temperature consistent with that of the heater chip's macroscopic heater/thermometer to within the 5\% accuracy of the chip thermometer's calibration. Thus silicon has the potential to provide its own, high-spatial-resolution thermometric readout signal via measurements of its volume plasmon energy. Furthermore, nanoparticles in general can serve as convenient nanothermometers for \emph{in situ} electron microscopy experiments.Comment: 6 pages, 3 figure
Thick In x Ga 1-x As metamorphic buffer layers (MBLs) grown by hydride vapor phase epitaxy (HVPE) were studied. Relationships between MBL properties and growth parameters such as grading rate, cap layer thickness, final x InAs , and deposition temperature (T D ) were explored. The MBLs were characterized by measurement of in-plane residual strain (ε || ), surface etch pit density (EPD), and surface roughness. Capping layer thickness had a strong effect on strain relaxation, with thickly capped samples exhibiting the lowest ε || . EPD was higher in samples with thicker caps, reflecting their increased relaxation through dislocation generation. ε || and EPD were weakly affected by the grading rate, making capping layer thickness the primary structural parameter which controls these properties. MBLs graded in discrete steps had similar properties to MBLs with continuous grading. In samples with identical thickness and 10-step grading style, ε || increased almost linearly with final x InAs , while total relaxation stayed relatively constant. Relaxation as a function of x InAs could be described by an equilibrium model in which dislocation nucleation is impeded by the energy of the existing dislocation array. EPD was constant from x InAs = 0 to 0.24 then increased exponentially, which is related to the increased dislocation interaction and blocking seen at higher dislocation densities. RMS roughness increased with x InAs above a certain strain rate (0.15%/μm); samples grown below this level possessed large surface hillocks and high roughness values. The elimination of hillocks at higher values of x InAs is attributed to increased density of surface steps and is related to the out-of-plane component of the burgers vector of the dominant type of 60 • dislocation. T D did not affect ε || for samples with a given x InAs . EPD tended to increase with T D , indicating dislocation glide likely is impeded at higher temperatures.
Monolithic integration of III-V nanowires on silicon platforms has been regarded as a promising building block for many on-chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one of the remaining challenges for on-chip applications is that the growth direction of nanowires on Si(001) substrates is difficult to control. Here, we propose and demonstrate catalystfree selective-area epitaxy of nanowires on ( 001)-oriented silicon-on-insulator (SOI) substrates with the nanowires aligned to desired directions. This is enabled by exposing {111} planes on (001) substrates using wet chemical etching, followed by growing nanowires on the exposed planes. We demonstrate the formation of nanowire array-based bottom-up photonic crystal cavities on SOI(001) and their coupling to silicon waveguides and grating couplers, which support the feasibility for onchip photonic applications. The proposed method of integrating position-and orientationcontrollable nanowires on Si(001) provides a new degree of freedom in combining functional and ultracompact III-V devices with mature silicon platforms.
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