Optimizing Radiation Hard by Design SRAM Cells

Clark, Lawrence T.; Mohr, K.C.; Holbert, Keith E.; Yao, Xiaoyin; Knudsen, J.E.; Shah, Hemanshi

doi:10.1109/tns.2007.909482

Cited by 41 publications

(21 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…There it was shown that by reducing the supply voltage and applying body bias techniques, a decrease of TID induced leakage current in a m CMOS n-channel device could be achieved. The reduction of TID induced leakage with reduced supply voltages has later also been verified for 130 nm [10], [11] and for 90 nm [12] CMOS technology nodes. The reason for the reduced impact of TID induced leakage at low supply voltages is the increased recombination of e-h pairs, and thereby less interface traps, in the absence of a strong electric field near the oxide [13].…”

Section: A Previous Workmentioning

confidence: 74%

Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

Hasanbegovic

Aunet

2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below cm bit (no SEUs detected) at 500 mV supply voltage, cm bit at 250 mV supply voltage, and cm bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least , and (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between MeV-cm mg and MeV-cm mg. Index Terms-Complimentary metal-oxide semiconductor (CMOS), flip-flop, low power, low voltage, radiation tolerant, single event transient (SET), single event upset (SEU).

show abstract

Section: A Previous Workmentioning

confidence: 74%

Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

Hasanbegovic

Aunet

2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…In this case, many contributions can be distinguished, but the main ones are the latch-up of the circuits and the single event effects (SEE). Some of these effects can be avoided by properly designing the circuits using radiation hardening-by-design techniques [8] - [9]. This is not the case for DDD effects related to the damaging of the crystalline structure of the substrate.…”

Section: Radiation Effects On Cmos and S-flash Cellmentioning

confidence: 99%

“…Three main approaches have been considered to develop rad-tolerant components: process enhancement (Radiation hardening-by-process, RHBP [2]), design enhancement (Radiation hardening-by-design, RHBD [3] ), and finally shielded packages. They can be of course combined to improve the rad-hard features.…”

Section: Introductionmentioning

confidence: 99%

SkyFlash EC project: Architecture for a 1Mbit S-Flash for space applications

Arbat

Calligaro

Dayan

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

View full text Add to dashboard Cite

This work presents an innovative architecture to fabricate a non volatile memory for space applications using a SFlash memory cell. The design takes into account the different effects of the radiation that could damage the circuits and the memory cell in harsh environments. The memory cell has been developed by TowerJazz Semiconductors to be compatible with the standard 180nm CMOS process. A 1Mbit prototype has been designed using the presented architecture.

show abstract

“…Triple-well technology also allows reverse-biasing of p-well to reduce the leakage currents ( ) induced by Total Ionizing Dose (TID) effects [2]. This approach has been used effectively in limiting the increases up to 1-2 Mrad total dose exposure for SRAM designs in 130 nm and 90 nm CMOS technologies [5].…”

Section: Introductionmentioning

confidence: 99%