Optimizing Power in Sequential Circuits by Reducing Leakage Current using Enhanced Multi Threshold CMOS

Sreenivasulu, P.; Rao, K. Ramakrishna; Babu, A. Vinaya

doi:10.17485/ijst/2016/v9i36/102601

Cited by 2 publications

(3 citation statements)

References 8 publications

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“…Sreenivasulu, et al (2016) [13] has presented the optimized sequential circuit to reduce the power leakage by multi threshold CMOS circuitry. This method designed to gives lower leakage current and offers upgraded speed.…”

Section: Literature Surveymentioning

confidence: 99%

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Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Kumar¹,

Madhavi²,

Kishore³

2022

JAMRIS

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Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

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Section: Literature Surveymentioning

confidence: 99%

“…The clock-gating method depends on inner halfway reconfiguration and topological changes. The arrangement depends on the powerful incomplete reconfiguration of the setup memory outlines identified with the clock steering assets [13].…”

Section: Introductionmentioning

confidence: 99%

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Kumar¹,

Madhavi²,

Kishore³

2022

JAMRIS

View full text Add to dashboard Cite

show abstract

“…The leakage feedback structure can be used instead, which does not slow down the critical path because no extra capacitances are introduced on internal nodes [12]. The addition of the helper sleep devices only add load to the outputs of I4 and I5 which are not part of the critical path, so the speed of the MTCMOS flip flop is not compromised.…”

Section: Leakage Feedback Static Flip Flopmentioning

confidence: 99%

Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

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Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold voltages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 -200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

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Optimizing Power in Sequential Circuits by Reducing Leakage Current using Enhanced Multi Threshold CMOS

Cited by 2 publications

References 8 publications

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Ultra-Low Power Designing for CMOS Sequential Circuits

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