Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Abstract

Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

“…The author analyzed the circuits in terms of delay, power and area and proved that gate based clock gating circuits are more power efficient [21] . A latchbased clock gating technique is used in the design of SRAM and sequential counter and verified the power reduction in the work [22] .…”

Approach to positional logic algebra

“…, for each conjunction, use (5) . (9) This example shows that the internal operators in complex positional operators serve to set the BF-prototypes of fragments, and the external ones set conjunctions that uniquely determine these fragments. Therefore, the complexity of positional operators in such representing in most does not exceed two, while maintaining their compactness.…”

“…According to representation (9), it is possible to build a flow graph of logic calculations (Fig. 1).…”

“…To expand its functionality, it is more efficient to increase the number of CBs in FBs. The regularity and scalability of the LC structure provide effective control the involvement in operation process its parts by using, for example, "operand isolation" technology [8,9]. This creates the prerequisites to change flexible the ratio between LC functionality, technical and economic parameters of the integral implementation, "bypassing" possible failures, increasing its reliability.…”

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

“…The main content of section 2 focuses on researching and presenting basic ideas about low power techniques. The various clock gating techniques including latch free clock gating, latchbased clock gating, data driven clock gating, data gating have been applied to various applications such SRAM, multiplier, ALU, digital signal processing, counter, linear feedback shift register, and so on [11][12][13][14][15][16]. This section also presents proposed hybrid clock gating and data gating techniques to get the most optimal results in terms of power, and comparing other low power techniques.…”