Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane Method

Tang, Wai Teng; Tan, Wen Jun; Krishnamoorthy, Rajagopal; Wong, Yi Wen; Kuo, Shyh-hao; Goh, Rick Siow Mong; Turner, Stephen J.; Wong, Weng-Fai

doi:10.1109/ipdps.2013.79

Cited by 12 publications

(8 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We also compare our results for the 3D stencil with the results reported in [10]. This work uses a different equation in which neighbor cells with the same distance from center share the same coefficient and hence, the FLOP per cell update for their stencil is lower.…”

Section: B Hardware and Software Setupmentioning

confidence: 78%

“…• We show that compared to the state-of-the-art YASK framework [9] on a modern Xeon and Xeon Phi Processor, and a recent GPU implementation [10], our FPGA implementation achieves better performance for 2D stencil computation, and competitive performance for 3D, and better power efficiency in almost all cases.…”

Section: Introductionmentioning

confidence: 90%

“…Even though there are multiple implementations of application-specific high-order stencils on different hardware, few of them discuss general optimization of such stencils. One of the recent examples on GPUs by Tang et al uses 2.5D spatial blocking (but no temporal blocking) and an "in-plane" optimization that allows them to achieve better memory alignment and coalescing compared to previous work, at the cost of extra redundant computation for each cell update [10]. They report performance for first to sixth-order stencils.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

Zohouri

Podobas

Matsuoka

2018

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

View full text Add to dashboard Cite

In this paper we evaluate the performance of FPGAs for high-order stencil computation using High-Level Synthesis. We show that despite the higher computation intensity and onchip memory requirement of such stencils compared to first-order ones, our design technique with combined spatial and temporal blocking remains effective. This allows us to reach similar, or even higher, compute performance compared to first-order stencils. We use an OpenCL-based design that, apart from parameterizing performance knobs, also parameterizes the stencil radius. Furthermore, we show that our performance model exhibits the same accuracy as first-order stencils in predicting the performance of high-order ones. On an Intel Arria 10 GX 1150 device, for 2D and 3D star-shaped stencils, we achieve over 700 and 270 GFLOP/s of compute performance, respectively, up to a stencil radius of four. These results outperform the state-of-theart YASK framework on a modern Xeon for 2D and 3D stencils, and outperform a modern Xeon Phi for 2D stencils, while achieving competitive performance in 3D. Furthermore, our FPGA design achieves better power efficiency in almost all cases.

show abstract

Section: B Hardware and Software Setupmentioning

confidence: 78%

Section: Introductionmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

Zohouri

Podobas

Matsuoka

2018

2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

View full text Add to dashboard Cite

show abstract

“…Some existing GPGPU auto-tuning works have used intelligent, nonexhaustive strategies [12-14, 20, 26]. However, all of this work (with the exception of Tang's which develops an analytical model to approximate performance [26]) focuses exclusively on a single optimization. In contrast, we consider multiple optimizations concurrently and our strategy takes into account the interactions amongst these optimizations.…”

Section: Related Workmentioning

confidence: 99%

A Strategy for Automatic Performance Tuning of Stencil Computations on GPUs

Garvey

Abdelrahman

2018

Scientific Programming

View full text Add to dashboard Cite

We propose and evaluate a novel strategy for tuning the performance of a class of stencil computations on Graphics Processing Units. The strategy uses a machine learning model to predict the optimal way to load data from memory followed by a heuristic that divides other optimizations into groups and exhaustively explores one group at a time. We use a set of 104 synthetic OpenCL stencil benchmarks that are representative of many real stencil computations. We first demonstrate the need for auto-tuning by showing that the optimization space is sufficiently complex that simple approaches to determining a high-performing configuration fail. We then demonstrate the effectiveness of our approach on NVIDIA and AMD GPUs. Relative to a random sampling of the space, we find configurations that are 12%/32% faster on the NVIDIA/AMD platform in 71% and 4% less time, respectively. Relative to an expert search, we achieve 5% and 9% better performance on the two platforms in 89% and 76% less time. We also evaluate our strategy for different stencil computational intensities, varying array sizes and shapes, and in combination with expert search.

show abstract

“…In recent times, Machine Learning (ML)–based autotuning systems are employed to determine the parameter space. These systems use a limited set of conventional parameters such as block size, shared memory size, number of registers to identify optimal values for the parameter space.…”

Section: Introductionmentioning

confidence: 99%

Autotuning of configuration for program execution in GPUs

Balaiah

Parthasarathi

2019

Concurrency and Computation

View full text Add to dashboard Cite

Summary Graphics Processing Units (GPUs) are used as accelerators for improving performance while executing highly data parallel applications. The GPUs are characterized by a number of Streaming Multiprocessors (SM) and a large number of cores within each SM. In addition to this, a hierarchy of memories with different latencies and sizes is present in the GPUs. The program execution in GPUs is thus dependent on a number of parameter values, both at compile time and runtime. To obtain the optimal performance with these GPU resources, a large parameter space is to be explored, and this leads to a number of unproductive program executions. To alleviate this difficulty, machine learning–based autotuning systems are proposed to predict the right configuration using a limited set of compile‐time parameters. In this paper, we propose a two‐stage machine learning–based autotuning framework using an expanded set of attributes. The important parameters such as block size, occupancy, eligible warps, and execution time are predicted. The mean relative error in prediction of different parameters ranges from of 16% to 6.5%. Dimensionality reduction for the features set reduces the features by up to 50% with further increase in prediction accuracy.

show abstract

Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane Method

Cited by 12 publications

References 18 publications

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

A Strategy for Automatic Performance Tuning of Stencil Computations on GPUs

Autotuning of configuration for program execution in GPUs

Contact Info

Product

Resources

About