Surface plasmon-coupled emission microscopy (SPCEM) was proposed as a high sensitivity technique that makes use of a thin layer of metal deposited on glass slides to efficiently excite fluorophores and to collect the emission light. However, the theoretical aspect of SPCEM imaging has not been well studied. We propose a model for SPCEM and show, through theoretical analysis and empirical results, that the point spread function of SPCEM is irregular and has an annular-like structure, significantly different from the familiar point spread function of the conventional wide-field microscopy. This result is due to the highly polarized and anisotropic emission caused by the metal layer.
Advances in non-volatile resistive switching random access memory (RRAM) have made it a promising memory technology with potential applications in low-power and embedded in-memory computing devices owing to a number of advantages such as low-energy consumption, low area cost and good scaling. There have been proposals to employ RRAM in architecting chips for neuromorphic computing and artificial neural networks where matrix-vector multiplication can be computed in the analog domain in a single timestep. However, it is challenging to employ RRAM devices in neuromorphic chips owing to the non-ideal behavior of RRAM. In this article, we propose a cycle-accurate and scalable system-level simulator that can be used to study the effects of using RRAM devices in neuromorphic computing chips. The simulator models a spatial neuromorphic chip architecture containing many neural cores with RRAM crossbars connected via a Network-on-Chip (NoC). We focus on system-level simulation and demonstrate the effectiveness of our simulator in understanding how non-linear RRAM effects such as stuck-at-faults (SAFs), write variability, and random telegraph noise (RTN) can impact an application's behavior. By using our simulator, we show that RTN and write variability can have adverse effects on an application. Nevertheless, we show that these effects can be mitigated through proper design choices and the implementation of a write-verify scheme. INTRODUCTIONNeuromorphic computing is a domain-specific computing approach that uses analog, digital, or mixed-mode integrated circuits to mimic biological architectures of the neural system, including neurons, axons, synapses, and dendrites [40]. Neurons whose inputs and outputs are spikes are used in neuromorphic computing; the resulting spike-based or spiking neural networks (SNNs) are often regarded as third-generation neural networks [39]. Special-purpose built hardware for neuromorphic computing includes the HiCANN chip [12], NeuroGrid [7], SpiNNaker [9], and IBM's TrueNorth chip [17]. SpiNNaker and TrueNorth are fully digital; HiCANN and NeuroGrid are analog or partially analog in design. In TrueNorth, 4096 neurosynaptic cores of size 256 × 256 are interconnected by an intra-chip network. Using TrueNorth to implement SNNs, Esser et al. demonstrated good accuracies in real-world application benchmarks [22].Concurrent with the developments in neuromorphic computing, advances in non-volatile resistive switching random access memory (RRAM) have made it a suitable memory technology for realizing neuromorphic computing architectures [11]. For instance, RRAM-based neuromorphic computing hardware has been proposed in [19,23,25]. Apart from advantages such as low operating power, high speed and density, memristive and RRAM-based crossbars have been proposed as energy-efficient dot-product engines. These can be used to perform matrix-vector multiplication operations efficiently in the analog domain through current sums [4,6,15]. Such approaches are suitable for low-power embedded devices targeting ne...
The effects of using radially polarized illumination in a confocal microscope are discussed, and the introduction of a polarization mode converter into the detection optics of the microscope is proposed. We find that with such a configuration, bright-field imaging can be performed without losing the resolution advantage of radially polarized illumination. The detection efficiency can be increased by three times without having to increase the pinhole radius and sacrificing the confocality of the system. Furthermore, the merits of such a setup are also discussed in relation to surface plasmon microscopy and single-molecule orientation studies, where the doughnut point spread function can be engineered into a single-lobed point spread function.
The sparse matrix-vector (SpMV) multiplication routine is an important building block used in many iterative algorithms for solving scientific and engineering problems. One of the main challenges of SpMV is its memory-boundedness. Although compression has been proposed previously to improve SpMV performance on CPUs, its use has not been demonstrated on the GPU because of the serial nature of many compression and decompression schemes. In this paper, we introduce a family of bit-representation-optimized (BRO) compression schemes for representing sparse matrices on GPUs. The proposed schemes, BRO-ELL, BRO-COO, and BRO-HYB, perform compression on index data and help to speed up SpMV on GPUs through reduction of memory traffic. Furthermore, we formulate a BRO-aware matrix reordering scheme as a data clustering problem and use it to increase compression ratios. With the proposed schemes, experiments show that average speedups of 1.5× compared to ELLPACK and HYB can be achieved for SpMV on GPUs.
The surface plasmon-coupled emission microscope provides high sensitivity for surface imaging. However, it suffers from a distorted donut-shape point-spread function (PSF). Here we report an effective yet simple method to correct for the distortion by introducing a spiral phase plate. This modification converts the donut PSF into one that is single lobed, which is preferable for imaging. The optical performance of the system is characterized and compared with previous publications. This technique provides more than twofold lateral resolution enhancement.
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