Optimized TSV process using bottom-up electroplating without wafer cracks

Lim, Byeong-Ok; Choi, Kwang-Seong; Eom, Yong‐Sung; Bae, Hae-Young; Jung, Sunghae; Sung, Ki-Jun; Moon, Jong-Tae

doi:10.1109/ectc.2010.5490762

Cited by 6 publications

(4 citation statements)

References 4 publications

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“…Any missing seed, for instance, could lead to plating issues. Detailed studies of copper plating problems, and ways to overcome them can be found in several recent publications [29,[33][34][35]37]. Further, annealing studies on the copper TSV have been conducted, and results reported in [42].…”

Section: Tsv Processesmentioning

confidence: 97%

“…polymers, followed by appropriate thermal processing and removal of excess material from the surface. Extensive work has been done in the development of each of these processes, and the characterization of the resulting TSV's at a variety of dimensions and pitches [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43].…”

Section: Tsv Processesmentioning

confidence: 99%

See 1 more Smart Citation

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Section: Tsv Processesmentioning

confidence: 97%

Section: Tsv Processesmentioning

confidence: 99%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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“…The conventional Cu electroplating cannot achieve defectless vertical deep via filling in 3D packaging. Since the copper electrodeposition rate at the deeper part of the microvia is smaller than that at the opening, resulting in voids at the bottom of the microvias [6]. To realise copper Figure 1 Fabrication process of the vertical vias fast-filling without voids into deep microvias, in this study we used a commercial electroplating solution (Model: UTP SYS-3320) including three electrolyte additives (accelerator, suppressor or leveller) from Sinyang [7].…”

Section: Cu Electroplating For Deep Blind-viasmentioning

confidence: 99%

Development of seed layer deposition and fast copper electroplating into deep microvias for three‐dimensional integration

Chen

2013

Micro & Nano Letters

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Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop towards three-dimensional integration using through a silicon via (TSV) copper interconnect. In this Letter, the key enabling technologies such as barrier and seed layers preparation by electron beam evaporation and copper fast-filling into deep microvias that are void-free are investigated. The deep vertical microvias filled by copper that are void-free are achieved by a multi-step electroplating process. Also, the resistance of single vertical TSVs is tested. Furthermore, the cross-sections and the scanning electron microscopy of vertical microvias are provided and examined.

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“…After the wafer thinning from initial thickness to 100μm, the wafer was sawed without any cracks. The individual TSV chips were 7 × 7 mm with 34 × 34 arrays [12]. Fig.…”

Section: Sbm Technologymentioning

confidence: 99%

Solder Bump Maker with coining process on TSV chips for 3D packages

Sung

Choi

Lim

et al. 2010

2010 11th International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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The electroplating and screen printing are widely used in the micro-electric industry but they have disadvantages of a complicated series of bumping process, equipments and materials. Furthermore, they are not suitable for the fine pitch bumping technology. To overcome these weak points, a maskless bumping technology using SBM has been developed. Solder Bump Masker (SBM) technology does not need any special equipment and mask tools. It is composed of solder powder and a resin. The solder is Sn58Bi and the resin is designed to have low viscosity for rheological characteristics of the solder droplets. In this paper, we optimized the bumping condition with controlling the process time. After bumping, the coining process, which the various loads were applied, has been investigated to get the bump with the extremely uniform heights. Finally, low-volume bumps with the excellent uniformity were successfully achieved.

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Optimized TSV process using bottom-up electroplating without wafer cracks

Cited by 6 publications

References 4 publications

3D integration review

3D integration review

Development of seed layer deposition and fast copper electroplating into deep microvias for three‐dimensional integration

Solder Bump Maker with coining process on TSV chips for 3D packages

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