Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

Jegadheesan, V.; Sivasankaran, K.; Konar, Aniruddha

doi:10.1109/ted.2020.3017175

Cited by 37 publications

(20 citation statements)

References 19 publications

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“…Figure 9 introduces various approaches to suppress the leakage current from the parasitic channel without the formation of a GP region [ 14 , 25 ]. A full bottom dielectric (FBD) can eliminate the parasitic channel perfectly ( Figure 9 a).…”

Section: Resultsmentioning

confidence: 99%

“…To elaborate, the dielectric constant of the HfO 2 gate dielectric and effective-oxide-thickness (EOT) were assumed to be 25 and 0.7 nm, respectively. In terms of doping concentration, epitaxially grown S/D regions were doped with arsenic at 3 × 10 20 cm −3 [ 14 , 23 ]. The three nanosheet channels and silicon substrate ( N Sub ) were lightly doped with boron at 1 × 10 17 cm −3 and 1 × 10 16 cm −3 , respectively.…”

Section: Methodsmentioning

confidence: 99%

“… Various device structures without a GP region. NS FET with ( a ) full bottom dielectric (FBD) [ 25 ], ( b ) super steep-retrograde (SSR) region [ 14 ], and ( c ) the proposed DUT layer. ( d ) Simulated I D - V G characteristics of the respective device structures.…”

Section: Figurementioning

confidence: 99%

“…Hence, even though NS FETs have multiple channels that are completely surrounded by metal gates (i.e., GAA), increased I OFF stemming from the parasitic channel is inevitable. V. Jegadheesan et al, have suggested that applying a ground plane (GP) region can effectively minimize the I OFF in the parasitic channel [ 14 ]. However, as we have mentioned above, the fabrication process flow of NS FETs is very sensitive.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Lee

Park

2022

Micromachines

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This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Six/SiGe1-x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.

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Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Lee

Park

2022

Micromachines

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“…Such a channel created in the lower substrate results in a high risk of leakage current in the 3 nm dimension. Ideas discussed to date to reduce such substrate leakage include: (i) inserting an insulating oxide layer for bottom isolation, which is referred to here as then bottom oxide (BO) scheme [4,5] and (ii) doping the bottom substrate, which is referred to as the punch-through-stopper (PTS) doping scheme [6,7]. While the PTS doping scheme and the bottom oxide (BO) scheme can be studied separately, there has been no analysis of simultaneous optimization to date.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

et al. 2022

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In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.

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Analytical analysis and linearity performance of dual metal high‐K Schottky nanowire FET(DM‐HK‐SNWFET)

Sharma

Nath

Deswal³

et al. 2023

Int J Numerical Modelling

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This study's objectives are to deliver a relative analysis of non‐uniformly doped (NUD) and uniformly doped Dual Metal High‐K Schottky nanowire FET (DM‐HK‐SNWFET). Surface potential, subthreshold current, subthreshold swing, and drain current have been expressed and analyzed by resolving 2D Poisson's equation with suitable boundary conditions. The analog performance of the device is verified by examining cut‐off frequency (fT), trans‐conductance frequency product (TFP), gain frequency product (GFP), and gain trans‐conductance frequency product (GTFP). The results show suitable RF circuit parameters with a high switching ratio (≈3 × 109) and low subthreshold swing (61 mV/decade) for NUD‐DM‐HK‐SNWFET. Additionally, linearity frequency of merits (FOMs) and distortion performance are also studied by numerically calculating higher order voltage and current intercept point (VIP2, VIP3, IIP3, IMD3); 1‐dB compression point and Harmonics distortions (HD2 and HD3) using transconductance (gm1) along with its higher derivatives gm2 and gm3. These parameters exhibit high‐level linearity and low‐level distortion at zero crossover points in NUD‐DM‐HK‐SNWFET, making it a better contender for low‐power and high‐performance applications.

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Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor

Cited by 37 publications

References 19 publications

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

Analytical analysis and linearity performance of dual metal high‐K Schottky nanowire FET(DM‐HK‐SNWFET)

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