Optimized placement of boundary scan circuitry on semi-custom ASICs

Buchner, T.

doi:10.1109/asic.1995.580715

Proceedings of Eighth International Application Specific Integrated Circuits Conference

DOI: 10.1109/asic.1995.580715

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Optimized placement of boundary scan circuitry on semi-custom ASICs

T. Buchner

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Boundary scan adaption for active substrate MCM-test

Werkmann

Höfflinger²,

Laquai³

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their eflects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan testsystems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.

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Boundary scan adaption for active substrate MCM-test

Werkmann

Höfflinger²,

Laquai³

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

View full text Add to dashboard Cite

show abstract

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Optimized placement of boundary scan circuitry on semi-custom ASICs

Cited by 1 publication

References 1 publication

Boundary scan adaption for active substrate MCM-test

Boundary scan adaption for active substrate MCM-test

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