Optimized load device for DMOS integrated circuits

Abstract

Depletion-mode load devices can be integrated with DMOS transistors without any extra diffusions or ion implantation processing steps by judicious choice of t h e s u b s t r a t e c r y s t a l o r i e n t a t i o n a n d r es i s t i v i t y . F o r l o w v o l t a g e o p e r a t i o n , ( l , l , l ) c r y stal orientation also yields a higher transconductance for the DMOS t r a n s i s t o r t h a n t h e (1, 0, 0 ) o r i e n t ation.The geometry of the load device and the DMOS t r a n s i s t o r c a n b e m a d e r a t i o l e s s t o c o n s e r v e a r e a . Self-aligned gates, hitherto considered incompatible with DMOS t r a n s i s t o r s , h a s b e e n i n c o r p o r a t e d i n t h e s t r u c t u r e .The experimental DMOS i n v e r t e r s , u s i n g a conservative design, have achieved 4 ns propagation delay, 1. 3V operation and 2 pJ propagation delaypower dissipation product. DMOS I n v e r t e rThe DMOS t r a n s i s t o r c a n be used in conjunction 1 with a d e p l e t i o n m o d e t r a n s i s t o r a s a n i n v e r t e r a s shown in Fig. 1. With double-diffused structures, it is feasible to integrate this kind of switching circuit. An integrated double-diffused n-channel MOS s t r u c t u r e i s s h o w n i n F i g u r e 2. T h e s u b s t r a t e i s of lightly-doped p-type or F-type. The window defining the source regions is diffused with both ntype dopant and a lower-concentration p-type dopant. The window defining the drain region is diffused with an n-type dopant as in conventional MOS t r a n sistors. The depletion mode load device can be obtained by eliminating the p-type diffusion for the active device as shown in Fig. 2. F o r s u c h a s t r u c t u r e , a p-type diffusion should also be applied to all the inactive areas to obtain isolation. Load Device T h e c h a r a c t e r i s t i c of the load device is dependent upon the substrate impurity concentration and t h e c r y s t a l o r i e n t a t i o n . F o r m o s t e c o n o m i c a l d esign, it i s d e s i r a b l e t h a t t h e g e o m e t r y of both the load device and the switch be minimum. The load device must be in depletion mode, i. e . , t h e t h r e shold voltage must be negative and is different from the zero-substrate-bias value because of t h e s u bstrate-bias or "body" effect. The threshold volta g e of a MOS t r a n s i s t o r o r l o a d d e v i c e i s g i v e n by the following relation w h e r e t h e f o l l o w i n g t e r m i n o l o g i e s a r e u s e d +GS= Gate-background work function difference = 7 n kT 4x10LUN(x) , (for an n-doped Si gate 9 2 n . with an assumed effective doping concentration of 4x1020 a t o m s / c m 3 ) ; n. = Intrinsic concentration = 1. 5x1O1O a t o m s / c m 3 at 27OC; NSS = S u r f a c e -s t a t e d e n s i t y ; + F = F e r m i l e v e l a s s o c i a t e d w i t h a given doping c o n c e n t r a t i o n s = -In -; kT N(x) 9 n i Cox = G a t e c a p a c i t a n c e p e r u n i t a r e a cox = D i e l e c t r i c c o n s t a n t of o x i d e = ( 4~8 . 8 5 x1...

Polysilicon Interconnection Technology for IC Device

“…The poly-Si of Si-gate MOS-LSI's is used not only for gate electrodes but also for interconnections. Therefore, poly-Si resistance has to be lowered to fabricate high speed MOS-LSI's (1).…”