Optimized layout for an EMC filter: Analysis and validations

Oliveira, Thomas De; Schanen, Jean‐Luc; Guichon, Jean‐Michel; Roudet, James

doi:10.1109/emceurope.2012.6396768

Cited by 11 publications

(3 citation statements)

References 16 publications

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“…Many efforts have been made to achieve automatic layout design for power modules [6,[12][13][14][15][16][17]. For example, Oliveira et al [18] and Martin et al [19] proposed automatic optimisations for the electromagnetic performance of an EMC filter and gate circuit, respectively, to achieve current balance. By using a fairly precise physical model, this approach saved considerable time compared to conventional design.…”

Section: Introductionmentioning

confidence: 99%

Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

Mei

Hao

Chen

et al. 2020

IET Power Electronics

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It is important to reduce both the size and parasitic of power modules when designing a layout. However, the layout design often relies on experience and was time-consuming. The problem is particularly prominent in silicon carbide (SiC) modules, which requires more parallel dye compared with silicon counterparts. In this study, an algorithm for multi-chip SiC module layout design automation is proposed, which combines genetic algorithm, candidate searching idea, parallel operation and simplified evaluation models for enhancing computational efficiency with reasonable accuracy. A 12-chip half bridge SiC module is studied to verify the feasibility of the proposed method. The results indicate the method is robust and efficient, and can generate optimal layouts with low parasitic inductance and resistance as well as small footprint. It is believed that the method is feasible to guide the automatic optimal layout design for multi-chip SiC modules, targeting small footprint and low parasitic.

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Section: Introductionmentioning

confidence: 99%

Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

Mei

Hao

Chen

et al. 2020

IET Power Electronics

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“…Metallized film capacitors are wildly used in power electronic applications, because of their low dielectric loss factor, their high voltage operating range and their self-healing capabilities [2][3] [4]. However, their performances and their bandwidth are reduced by their stray inductance, mostly due to the connections of the capacitor with electrical circuit devices [5][6] [7]. As those capacitors are commonly used for decoupling function in power converters, it is necessary to take an interest in the layout of their connections in order to minimize their stray inductance [8] [9][6] [10].…”

mentioning

confidence: 99%

Optimization of Metalized Film Capacitor Connection to Reduce Stray Inductance

Penven

Martin

Joubert

et al. 2019

IEEE Trans. Compon., Packag. Manufact. Technol.

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Régis Meuret, et al.. Optimization of metallized film capacitor connection to reduce stray inductance. IEEE Transactions on Components Packaging and Manufacturing Technology Part B, Institute of Electrical and Electronics Engineers (IEEE), 2018, pp. AbstractIn power electronic applications, due to switching components, the inverter dc-bus generates current pulses at low and high frequencies.Usually, a dc-bus capacitor is sized to absorb the current peaks at the switching frequency, and to stabilize the DC voltage. For decoupling the high frequency (HF) harmonics, an additional capacitor is required. This decoupling capacitor needs to have a low impedance over a wide range of frequencies. However, their performances for the high frequency range are highly limited by their stray inductance. In order to minimize the need for an additional decoupling capacitor at high frequencies, this paper proposes to improve the connections of the DC bus capacitor. Busbar configuration and Printed Circuit Board (PCB) allow reducing parasitics of the cabling. Several types of interconnection are proposed and characterized in this study. Both 2-terminal and 4-terminal capacitors are evaluated and compared regarding operating frequency ranges. Measurement and modeling results show a significant improvement for HF decoupling by using quadrupole coaxial connections.

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“…There have been presented various measurement techniques for mutual coupling measurement [2], [1], extraction [3], mutual coupling reduction [4] and optimization [5] - [7]. Therefore, there is lack of information on techniques and possibilities, using in market available, the most popular 3D electromagnetic modeling tools that could help in more effective manner to solve these problems.…”

mentioning

confidence: 99%

Capacitors mutual inductance modeling and reduction

Asmanis

Stepins

Asmanis

et al. 2014

2014 International Symposium on Electromagnetic Compatibility

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In this paper modeling of EMI filter capacitors and modeling of mutual couplings between them is presented. The modeling has been done using 3D electromagnetic software CST MWS. Three capacitor models have been proposed and verified experimentally. All proposed models during verification have shown that their performance is high enough to enable PCB mounted capacitor modeling and mutual inductance modeling between capacitors. Additionally several mutual inductance reduction techniques have been proposed, measured and modeled.

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Optimized layout for an EMC filter: Analysis and validations

Cited by 11 publications

References 16 publications

Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

Efficient layout design automation for multi‐chip SiC modules targeting small footprint and low parasitic

Optimization of Metalized Film Capacitor Connection to Reduce Stray Inductance

Capacitors mutual inductance modeling and reduction

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